LTC2261IUJ-14 - 14-Bit 125Msps Ultra-Low Power 1.8V ADC | ADI
부품 번호: LTC2261IUJ-14 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.25 | $382.50 |
| 100 | $33.95 | $3,395.00 |
| 500 | $30.1 | $15,050.00 |
| 1,000 | $26.8 | $26,800.00 |
LTC2261IUJ-14 개요
A pipelined ADC is a high-speed successive-approximation architecture that breaks the conversion into multiple low-resolution stages operating in parallel on different clock edges, enabling sample rates of tens to hundreds of Msps while keeping per-stage power dissipation low. The LTC2261IUJ-14 targets AC performance, featuring 73.4 dB SNR and 85 dB spurious-free dynamic range (SFDR), which makes it well-suited to communications and signal-intelligence front-ends where wide dynamic range signals must be digitized cleanly.
Key specifications include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over the full operating temperature range, and 1.2 LSB RMS transition noise. The digital output port is highly flexible, supporting full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS modes, and a separate output power supply pin (OVDD) allows the CMOS swing to be programmed from 1.2 V to 1.8 V for direct interface to 1.2 V, 1.5 V, or 1.8 V logic.
The 'UJ-14' ordering code combines the industrial temperature grade (-40 °C to +85 °C) with the 40-lead QFN (6x6) package and a 14-bit resolution. The part is part of Linear Technology's classic low-power 1.8 V ADC portfolio that was later absorbed into the Analog Devices data-converter catalog after the 2017 ADI/LTC merger, with datasheet document 226114fc.
Typical applications include communications receivers, cellular base-station IF sampling, cable-headend digitizers, medical imaging front-ends, portable instrumentation, and non-destructive test equipment. Its ultra-low 1.8 V analog supply operation (~100 mW typical at 125 Msps) also makes it attractive for low-power field-deployed systems.
When designing with the LTC2261IUJ-14, drive the analog inputs with a low-noise, wideband differential amplifier such as the AD8138 or LT1994 to realize the datasheet SNR/SFDR. Use a low-jitter differential clock source and provide well-decoupled AVDD and OVDD rails; the exposed pad must be soldered to a continuous ground plane for thermal and electrical performance.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical layout notes that go beyond the manufacturer datasheet, giving engineers a single reference for sourcing and designing with the LTC2261IUJ-14.
드롭인 대체품: LTC2261IUJ-14 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2261IUJ-14 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Power-Saving Modes, Resolution, Transition Noise, Configuration Interface.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2260IUJ-14
✅ 드롭인✓ 재고 있음
$20.95 / 개
데이터시트 보기 →LTC2259IUJ-14
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2261CUJ-14
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$43.96 / 개
데이터시트 보기 →LTC2260CUJ-14
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$19.4 / 개
데이터시트 보기 →LTC2258IUJ-14
✅ 드롭인✓ 재고 있음
$15.05 / 개
데이터시트 보기 →LTC2261IUJ-14 최대 정격 & 전기적 특성
| 분해능 | 14 bits |
| Sample Rate | 125 Msps |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Input Type | Differential (single-ended capable with biasing) |
| Analog Supply Voltage (AVDD) | 1.8 V |
| Output Supply Voltage (OVDD) | 1.2 V to 1.8 V |
| Integral Nonlinearity (INL) | ±1 LSB (typical) |
| Differential Nonlinearity (DNL) | ±0.3 LSB (typical) |
| Transition Noise | 1.2 LSB RMS |
| Signal-to-Noise Ratio (SNR) | 73.4 dB |
| Spurious-Free Dynamic Range (SFDR) | 85 dB |
| Missing Codes | None over temperature |
| Digital Output Modes | Full-rate CMOS, DDR CMOS, DDR LVDS |
| 동작 온도 범위 | -40 °C to +85 °C (I grade) |
| 패키지 | 40-pin QFN (6x6 mm) with exposed pad |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant (PBF suffix) |
LTC2261IUJ-14 핀 구성
| 핀 1 | AINM — Differential analog input negative |
| 핀 2 | AINP — Differential analog input positive |
| 핀 3 | GND — Analog ground reference |
| 핀 4 | AVDD — 1.8 V analog supply |
| 핀 5 | GND — Analog ground |
| 핀 6 | VCM — Common-mode voltage output (mid-rail reference) |
| 핀 7 | CLKM — Differential clock input negative |
| 핀 8 | CLKP — Differential clock input positive |
| 핀 9 | GND — Clock ground |
| 핀 10 | OVDD — Output driver supply (1.2 V to 1.8 V) |
| 핀 11 | D0 — Digital data output bit 0 (LSB) |
| 핀 12 | D1 — Digital data output bit 1 |
| 핀 13 | D2 — Digital data output bit 2 |
| 핀 14 | D3 — Digital data output bit 3 |
| 핀 15 | D4 — Digital data output bit 4 |
| 핀 16 | D5 — Digital data output bit 5 |
| 핀 17 | D6 — Digital data output bit 6 |
| 핀 18 | D7 — Digital data output bit 7 |
| 핀 19 | D8 — Digital data output bit 8 |
| 핀 20 | D9 — Digital data output bit 9 |
| 핀 21 | D10 — Digital data output bit 10 |
| 핀 22 | D11 — Digital data output bit 11 |
| 핀 23 | D12 — Digital data output bit 12 |
| 핀 24 | D13 — Digital data output bit 13 (MSB) |
| 핀 25 | OF — Overflow / out-of-range indicator |
| 핀 26 | OR — Out-of-range (combined over/under) |
| 핀 27 | GND — Digital ground |
| 핀 28 | MODE — Output mode select (CMOS / LVDS) |
| 핀 29 | CS — Chip select / serial interface enable |
| 핀 30 | SCK — Serial configuration clock |
| 핀 31 | SDI — Serial configuration data input |
| 핀 32 | SDO — Serial configuration data output |
| 핀 33 | GND — Digital ground |
| 핀 34 | OVDD — Output driver supply |
| 핀 35 | GND — Digital ground |
| 핀 36 | DNC — Do not connect (per datasheet) |
| 핀 37 | DNC — Do not connect (per datasheet) |
| 핀 38 | DNC — Do not connect (per datasheet) |
| 핀 39 | DNC — Do not connect (per datasheet) |
| 핀 40 | DNC — Do not connect (per datasheet) |
일반적인 애플리케이션
LTC2261IUJ-14 적합 용도: 6 애플리케이션s: Cellular Base-Station IF Sampling, Communications Receiver Digitizer, Medical Imaging Front-End, Portable Test & Measurement Instrumentation, Cable Headend / QAM Digitizer, Industrial Non-Destructive Testing (NDT) Equipment.
Cellular Base-Station IF Sampling
The LTC2261IUJ-14's 73.4 dB SNR and 85 dB SFDR at 125 Msps suit multi-carrier IF digitization in 3G/4G/5G base-station receivers. Differential analog inputs (AINP/AINM) accept IF signals from the mixer stage, and DDR LVDS output minimizes EMI on the long backplane trace to the FPGA/ASIC. The 1.8 V analog supply simplifies power-rail design, while the separate OVDD pin allows direct 1.2 V/1.5 V/1.8 V logic interfacing without level shifters. Compared to slower 80 Msps ADCs, the LTC2261IUJ-14 captures wider IF bandwidth and provides more headroom for digital downconversion.
추천
Communications Receiver Digitizer
Wide-band communications receivers need high dynamic range at baseband or low-IF to demodulate weak signals in the presence of strong blockers. The LTC2261IUJ-14's pipelined architecture delivers 73.4 dB SNR for clean demodulation, while the 1.2 LSB RMS transition noise preserves small-signal resolution. Drive the analog inputs with a low-noise differential amplifier such as the AD8138 or LT6600 to maintain SFDR. The exposed-pad 40-QFN package provides a low thermal resistance path, enabling reliable operation in fanless outdoor radio units.
추천
Medical Imaging Front-End
Ultrasound and other medical imaging front-ends digitize filtered transducer signals at tens of Msps with high SNR. The LTC2261IUJ-14's 73.4 dB SNR and 125 Msps sample rate support multi-channel beamforming systems where per-channel dynamic range directly affects image quality. The 1.8 V analog supply reduces patient-side thermal dissipation in compact cart-based systems, and the LVDS output mode minimizes digital crosstalk into adjacent analog traces on densely populated medical boards.
추천
Portable Test & Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data-acquisition modules need low power consumption to maximize battery life. The LTC2261IUJ-14's ultra-low 1.8 V operation (~100 mW at 125 Msps) extends runtime in field-deployed instruments, while its 14-bit resolution and 73.4 dB SNR support accurate measurement of moderate-bandwidth signals up to 60 MHz. The flexible CMOS/LVDS output simplifies interfacing to both low-cost microcontrollers and high-speed FPGAs, and the 40-QFN package fits easily into compact handheld enclosures.
추천
Cable Headend / QAM Digitizer
Cable-TV headend equipment digitizes multiple QAM carriers spanning MHz-wide spectrum blocks for downstream processing. The LTC2261IUJ-14's 85 dB SFDR is critical to prevent weak carriers from being masked by intermodulation spurs of strong ones, and 125 Msps sample rate provides adequate oversampling for the cable band plan. The 40-QFN exposed-pad package enables dense multi-channel receiver cards, and the LVDS output keeps the long backplane trace EMI-compliant with the headend chassis standards.
추천
Industrial Non-Destructive Testing (NDT) Equipment
Ultrasonic flaw detectors and eddy-current NDT instruments digitize broadband transducer signals with high dynamic range to reveal sub-surface defects. The LTC2261IUJ-14's 1.2 LSB RMS transition noise and no-missing-codes over-temperature behavior preserves small reflection amplitudes, while the 125 Msps rate captures the full bandwidth of high-frequency probes. The industrial -40 °C to +85 °C operating range covers harsh factory-floor deployments, and the 1.8 V supply simplifies battery-powered portable flaw detectors.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2261IUJ-14 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2260IUJ-14 | LTC2259IUJ-14 | LTC2261CUJ-14 | LTC2260CUJ-14 | LTC2258IUJ-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Sample Rate | 125 Msps | 105 Msps | 80 Msps | 125 Msps | 105 Msps | 65 Msps |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Output Modes | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
| Temperature Range | -40 to +85 C (I grade) | -40 to +85 C | -40 to +85 C | 0 to +70 C (C grade) | 0 to +70 C (C grade) | -40 to +85 C |
주요 차별점
- 125 Msps speed grade in the 1.8 V ultra-low-power family (vs LTC2260IUJ-14)
- Wide digital-interface flexibility on the same die (vs LTC2259IUJ-14)
- Industrial -40 to +85 C temperature grade (vs LTC2261CUJ-14)
설계 노트
Solder the exposed thermal pad of the 40-QFN package to a continuous, low-impedance ground plane using an array of thermal vias. This serves both as the primary heat-dissipation path (the ADC draws ~100 mW at 125 Msps) and as the electrical ground reference for the analog inputs. Avoid routing signal traces under the package, and place the input capacitors for AVDD and OVDD within 3 mm of their respective supply pins with a ground return via directly beneath the capacitor pad.
Drive the AINP/AINM analog inputs differentially with a low-noise, wideband amplifier such as the AD8138 or LT6600 to realize the datasheet 73.4 dB SNR and 85 dB SFDR. Use a transformer-coupled drive (e.g., ADT1-1WT) for the highest-SFDR applications, and place the input common-mode capacitor (typically 10 nF) close to the ADC pins. For the CLK+/CLK- differential sample clock, use a low-jitter clock source (e.g., LTC6957) and route the clock traces as a 100 ohm differential pair away from the analog input traces.
Use separate analog (AVDD) and digital (OVDD) supply rails, each decoupled with a 10 uF bulk capacitor plus 100 nF and 10 nF ceramic capacitors placed as close to the supply pins as possible. The 1.8 V AVDD rail should be generated by a low-noise LDO (e.g., LT3042) downstream of the main switching regulator, and OVDD can range from 1.2 V to 1.8 V to match the host logic level. Star-ground the analog and digital grounds at the ADC exposed pad to prevent digital return currents from corrupting the analog ground reference.
Do not leave the MODE pin floating - it selects between CMOS and LVDS output modes and must be tied to a logic level (typically GND for LVDS or OVDD for CMOS) for proper operation. Do not exceed the maximum AVDD of 1.9 V; the ADC is a 1.8 V part and absolute-maximum violations can permanently damage the device. The CS/SCK/SDI/SDO serial interface pins are used to read the internal mode register, not to configure the part - configuration is done via the MODE pin and dedicated configuration pins at power-up.
규정 준수 정보
RoHS-compliant per #PBF suffix. AEC-Q100 not applicable - this is a data converter, not an automotive-qualified IC. Industrial temperature grade -40 to +85 C.
