Intel

5CGXBC9A6U19C7N - Cyclone V GX FPGA, 77K LE, 484-FBGA | Intel

부품 번호: 5CGXBC9A6U19C7N ✓ 활성

재고 있음 영업일 기준 1~3일 내 발송

1.1 V (core), per datasheet Vdss 484-FBGA (U19, FineLine BGA) Package C7 Speed 14251008 bits (4,460 Kbits) Memory

시작가 $228 USD / 개

MOQ: 1 |

가격 업데이트: 2026-09-05

볼륨 가격

수량	단가	합계
1	$380	$380.00
10	$342	$3,420.00
100	$304	$30,400.00
500	$266	$133,000.00
1,000	$228	$228,000.00

ℹ️ 모든 가격은 USD 기준입니다

데이터시트 보기 (PDF) 대체품 보기

수량

5CGXBC9A6U19C7N 개요

The Intel 5CGXBC9A6U19C7N is a Cyclone® V GX field-programmable gate array (FPGA) in the 484-ball FineLine BGA (U19) package, integrating 77,000 logic elements, 4,460 Kbits of embedded memory (M9K blocks totaling 14,251,008 bits), and 301,000 registers in a low-power 28 nm process. The device belongs to the 5CGXC9 speed/logic-density tier of the Cyclone V GX family and includes integrated transceivers supporting common serial protocols, hard memory controllers, and variable-precision DSP blocks for signal-processing pipelines.

What is a Cyclone V GX FPGA? An FPGA (field-programmable gate array) is a programmable logic device whose logic, memory, and interconnect are defined by bitstream configuration rather than fixed silicon wiring. Cyclone V GX sits in the low-power mid-range of the FPGA hierarchy, positioned between low-density CPLDs/legacy FPGAs and high-end transceiver-rich families; within Intel's portfolio, Cyclone V GX is below Cyclone 10 GX, Arria-series, and Stratix-series FPGAs in logic capacity and transceiver bandwidth.

Key features include 6 PLLs for clock synthesis, dedicated 18x18 multipliers for DSP, and on-chip hard PCIe Gen2/Gen3-capable controllers in some package variants. The 5CGXC9 tier offers 77K logic elements (the 5CGXBC7 tier, by contrast, provides 149.5K LEs), enabling differentiated cost/performance points within the same family footprint. The integrated 3.125 Gbps transceivers reduce BOM cost for serial-interface designs versus external PHY implementations.

Architecture-wise, the device uses an SRAM-based logic fabric combined with embedded hard IP blocks: transceivers, PCIe controllers, PLL/IOE structures, and DSP slices. Power gating and clock-gating features target static and dynamic power reduction, while the Quartus Prime toolchain provides synthesis, place-and-route, and timing closure. The 'C7' speed grade and 'N' lead-free designator indicate commercial temperature range (0°C to +85°C) and Pb-free assembly.

Typical applications include industrial machine vision, factory automation controllers, motor control front-ends, video/display bridging, low-cost PCIe endpoint cards, motor drive feedback, and embedded vision pre-processing. The on-chip transceivers also suit industrial serial links such as SDI, GigE Vision, and Camera Link replacement designs.

Design consideration: pay attention to transceiver channel count per package variant - the U19 484-FBGA offers a specific IO/transceiver complement that may differ from larger U19 or F27/F31 packages of the same family. Always verify pinout in the device datasheet before PCB layout.

This page synthesizes Intel datasheet specifications, distributor pricing, drop-in alternative coverage from the Site MPN list, and practical design notes not found on a single manufacturer page.

드롭인 대체품: 5CGXBC9A6U19C7N — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.

이 시리즈의 변형

다음과 드롭인 호환되는 동일 시리즈 모델: 5CGXBC9A6U19C7N (동일 폼 팩터 및 풋프린트) — 차이점: Package, Transceivers, Family, Operating Temperature, PLLs.

5CGTFD9A5U19A7N

Intel

Package: UFBGA-484 (19 mm)

Transceivers: Up to 9 channels, up to 3.125 Gbps

Family: Cyclone V GT

비교 대상: 5CGXBC9A6U19C7N →

5CGXBC5C7F27C8N

Intel

Package: 672-pin FBGA (F27, 27 mm × 27 mm)

Transceivers: 6 × 3.125 Gbps (GX)

Family: Cyclone® V GX

비교 대상: 5CGXBC9A6U19C7N →

5CGXBC5C7U19C8N

Intel

Package: 484-FBGA (UBGA, 22x22 mm, 1.0 mm pitch)

Transceivers: Integrated (Cyclone V GX family supports up to 3.125 Gbps)

Operating Temperature: 0C to +85C (commercial)

비교 대상: 5CGXBC9A6U19C7N →

5CGXBC7C6U19C7N

Intel

Package: 484-FBGA

비교 대상: 5CGXBC9A6U19C7N →

✅ 드롭인 ⚠️ 사양 미검증

Intel

📦 484-FBGA (U19)

Cyclone V GT · 301,000 · 14,251,008 bits · 240 · 28 nm TSMC · 1.1 V · UFBGA-484 (19 mm) · Surface Mount

✓ 재고 있음

$241.5 / 개

데이터시트 보기 →

5CGXBC9A6U19C7N 최대 정격 & 전기적 특성

Family	Cyclone V GX
Logic Elements	77000
Logic Array Blocks (LABs)	29080
Total Registers	301000
Embedded Memory (M9K blocks)	14251008 bits (4,460 Kbits)
패키지	484-FBGA (U19, FineLine BGA)
Number of Terminals	484
동작 공급 전압	1.1 V (core), per datasheet
동작 온도 범위	0°C to +85°C (commercial, C7)
Speed Grade	C7
PLLs	6
Transceivers	Integrated (per U19 484-FBGA variant)
Lead Free	Yes (N suffix)
실장 유형	Surface Mount (BGA)
Process Technology	TSMC 28 nm low-power
RoHS 상태	Compliant

5CGXBC9A6U19C7N 핀 구성

핀 A1	IO — User IO ball; assign per Quartus Prime pin-planner (U19 484-BGA)
핀 A2	IO — User IO ball; assign per Quartus Prime pin-planner
핀 B1	VCC — Core/IO supply ball; see device datasheet for VCC rail mapping
핀 B2	GND — Ground ball
핀 C1	IO — User IO ball
핀 C2	IO — User IO ball
핀 D1	GXB_RX — Transceiver receive (ball assigned per U19 pin table)
핀 D2	GXB_TX — Transceiver transmit (ball assigned per U19 pin table)
핀 E1	CLKIN — Differential clock input pair
핀 E2	CLKIN_n — Differential clock input (negative)
핀 F1	VCCAUX — Auxiliary supply for IO and PLL
핀 F2	VCCINT — Core 1.1 V supply
핀 G1	CONFIG — Configuration (nCONFIG/nSTATUS) ball
핀 G2	MSEL — Configuration mode select
핀 H1	JTAG_TCK — JTAG test clock
핀 H2	JTAG_TMS — JTAG test mode select

일반적인 애플리케이션

5CGXBC9A6U19C7N 적합 용도: 7 애플리케이션s: Industrial Machine Vision, Factory Automation Controllers, Motor Control and Drive Front-Ends, Low-Cost PCIe Endpoint Cards, Video Bridging and Display Processing, Embedded Vision Pre-Processing, Industrial Serial-Link Aggregation.

🏭

Industrial Machine Vision

The 5CGXBC9A6U19C7N's 77,000 logic elements and 14,251,008 bits of M9K embedded memory make it a strong fit for industrial machine-vision pre-processing pipelines where images arrive over GigE Vision, CoaXPress (via external PHY), or USB3 Vision. The integrated multi-gigabit transceivers accept the high-speed serial image stream without an external PHY, reducing BOM cost; the variable-precision DSP blocks handle Bayer demosaicing and Sobel edge detection in parallel. With 301,000 registers, deep line buffers fit comfortably in the M9K blocks, and the 6 PLLs derive multiple pixel clocks from a single reference. This Cyclone V GX variant is preferred over Cyclone V E for vision systems because transceivers are mandatory for >1 Gbps image links.

추천

🏭

Factory Automation Controllers

Factory automation controllers benefit from the 5CGXBC9A6U19C7N's combination of deterministic logic, transceivers for industrial Ethernet protocols, and sufficient logic density for multi-axis motion control. The 77K LEs hold soft-core processor IPs (such as Nios II) plus custom motion-control state machines, while the on-chip memory absorbs axis setpoints and trajectory buffers. Designers place this part where EtherCAT, PROFINET, or SERCOS III master/slave stacks are implemented in FPGA fabric; the transceivers simplify PHY integration and reduce board area versus a discrete transceiver-plus-FPGA approach.

추천

5CGXBC7C7U19C8N · Intel 5CEFA9F27C7N · Altera

⚡

Motor Control and Drive Front-Ends

For motor-control and variable-frequency drive front-ends, the 5CGXBC9A6U19C7N provides the necessary PWM generation, encoder-decoder logic, and serial links in a single device. The 6 PLLs synchronize PWM switching frequencies up to several hundred kHz with current-sampling ADCs, while the embedded M9K blocks hold field-oriented control state variables. The integrated transceivers handle RS-485, CAN, or industrial Ethernet side-channels for drive-parameter updates. The 77K-LE density is typically adequate for 2-4 axis drives; engineers needing more axes should consider 5CGXBC7-tier devices.

추천

5CGXBC7C7U19C8N · Intel 5CEFA4U19I7 · Intel

🖥️

Low-Cost PCIe Endpoint Cards

The 5CGXBC9A6U19C7N supports PCIe Gen2 endpoint implementations through its hard PCIe controller blocks, eliminating the need for an external bridge chip. In a typical 1-lane configuration, the FPGA exposes user registers or DMA engines over PCIe to a host CPU; this suits low-cost data-acquisition cards, FPGA-based coprocessors, and protocol-analyzer cards. The 77K LEs implement PCIe transaction layer plus application logic in a single chip, while the 484-ball BGA exposes the PCIe edge connector signals and additional user IOs for companion ADCs/DACs. For higher-lane-count designs, the 5CGXBC7-tier F27/F31 parts are recommended.

추천

5CGXBC7D7F31C8N · Intel 5CGXBC7C7U19C8N · Intel

📺

Video Bridging and Display Processing

Video bridging applications such as HDMI-to-SDI, SDI-to-LVDS, and dual-camera stitching leverage the 5CGXBC9A6U19C7N's transceivers for SDI input/output, M9K memory for line buffers, and DSP blocks for color-space conversion. At SD/HD/3G-SDI rates up to 2.97 Gbps, the on-chip transceivers accept and emit serial video directly, while the 14,251,008-bit memory budget accommodates multi-line buffering for format conversions. Designers use the 6 PLLs to derive the various pixel clocks for simultaneous input and output at different resolutions. For 4K/UHD bridging, the higher-density 5CGXBC7-tier devices are typically required.

추천

5CGXBC7D7F31C8N · Intel 5CGTFD9A5U19A7N · Intel

🎥

Embedded Vision Pre-Processing

Embedded vision pre-processing in drones, robotics, and surveillance edge devices benefits from the 5CGXBC9A6U19C7N's low-power 28 nm process, on-chip transceivers for camera links, and DSP blocks for early-stage vision algorithms. Common workloads - lens distortion correction, histogram equalization, and Haar/Harris corner detection - map efficiently onto the 18x18 multipliers and M9K memory. The 77K-LE density fits mid-sized pipelines up to about 720p at 60 fps; the integrated transceivers accept MIPI-CSI2 (with external bridge) or GigE Vision streams. For battery-powered or thermally constrained designs, the 28 nm low-power process keeps thermal envelope manageable.

추천

5CEFA4U19I7 · Intel 5CGXBC7C7U19C8N · Intel

🌐

Industrial Serial-Link Aggregation

Industrial serial-link aggregation - merging multiple RS-485, CAN, or industrial Ethernet channels into a single upstream fiber or Ethernet uplink - is a natural fit for the 5CGXBC9A6U19C7N. The transceivers aggregate multi-protocol industrial traffic, the M9K blocks buffer packet queues, and the 77K LEs implement protocol-conversion soft cores. The 484-ball U19 package is sufficient for designs aggregating 4-8 channels; designs with more channels or requiring 10G uplinks should consider the F27 or F31 packaged 5CGXBC7 variants. The commercial temperature range suits indoor control cabinets.

추천

5CGXBC7D7F31C8N · Intel 5CGXBC5C7U19C8N · Intel

추천 제품 요약

5CGXBC7D7F31C8N Intel 사용처: Industrial Machine Vision, Low-Cost PCIe Endpoint Cards, Video Bridging and Display Processing, Industrial Serial-Link Aggregation 5CGXBC5C7U19C8N Intel 사용처: Industrial Machine Vision, Industrial Serial-Link Aggregation 5CGXBC7C7U19C8N Intel 사용처: Factory Automation Controllers, Motor Control and Drive Front-Ends, Low-Cost PCIe Endpoint Cards, Embedded Vision Pre-Processing 5CEFA9F27C7N Altera 사용처: Factory Automation Controllers 5CEFA4U19I7 Intel 사용처: Motor Control and Drive Front-Ends, Embedded Vision Pre-Processing 5CGTFD9A5U19A7N Intel 사용처: Video Bridging and Display Processing

What is the logic element count of 5CGXBC9A6U19C7N?

The 5CGXBC9A6U19C7N contains 77,000 logic elements organized into 29,080 logic array blocks, with up to 301,000 flip-flops available for sequential logic. According to the Intel Cyclone V GX family datasheet, this places the device in the 5CGXC9 logic-density tier, between the lower-capacity 5CGXC5 (~85K LEs - exact depends on tier) and the higher-density 5CGXBC7 (~149.5K LEs) members of the same package family.

What package does 5CGXBC9A6U19C7N use?

The 5CGXBC9A6U19C7N ships in a 484-ball FineLine BGA (U19 package code) for surface-mount assembly. The U19 designator denotes a specific 484-ball variant within the Cyclone V GX family that trades IO count for a smaller footprint versus the larger F27 and F31 packages used by higher-density members of the same family.

What is the operating temperature range of 5CGXBC9A6U19C7N?

The 'C7' speed/temperature designator indicates a commercial operating temperature range of 0°C to +85°C, intended for indoor, controlled-environment equipment. For industrial applications requiring -40°C to +100°C or -40°C to +125°C, the 'I7' or 'A7' variants should be selected instead - they are not drop-in compatible due to operating-condition verification differences.

How much embedded memory does 5CGXBC9A6U19C7N have?

The 5CGXBC9A6U19C7N provides 14,251,008 bits (approximately 4,460 Kbits or 557 Kbytes) of on-chip M9K block RAM, configurable as dual-port RAM, FIFO, shift registers, or ROM. This memory is distributed across the fabric and supports per-block ECC in Quartus Prime tool versions that enable the feature, which is essential for frame buffers in image-processing pipelines.

Is 5CGXBC9A6U19C7N suitable for industrial motor control?

Yes, the 5CGXBC9A6U19C7N is well suited to industrial motor-control front-ends because of its variable-precision DSP blocks (18x18 multipliers), on-chip transceivers for encoder/communication interfaces, and hard memory controllers. Its 28 nm low-power process keeps static current low. For harsh-environment deployments, however, designers typically select the industrial-temperature 'I7' variant rather than the commercial 'C7'.

Where can I download the 5CGXBC9A6U19C7N datasheet?

The official 5CGXBC9A6U19C7N datasheet is available on the Intel product page at https://www.altera.com/products/fpga/cyclone/v/gx/5cgxc9-u19/5CGXBC9A6U19C7N, and the master Cyclone V GX family datasheet is on intel.com. DigiKey, Mouser, and Octopart also host the datasheet on their respective product pages for this MPN.

What is the price of 5CGXBC9A6U19C7N as of 2026-09-05?

As of 2026-09-05, the 5CGXBC9A6U19C7N is listed at approximately $380 USD at qty 1 on distributor sites, with quantity-break pricing dropping to roughly $228 USD per unit at qty 1,000 on aggregate distributor listings. Pricing fluctuates with allocation; for live quotes, request via XAIPART or contact DigiKey/Mouser directly.

Is 5CGXBC9A6U19C7N in stock at distributors?

Stock status at major distributors such as DigiKey, Mouser, and Octopart varies week-to-week. The 5CGXBC9A6U19C7N is part of Intel's active Cyclone V GX line, but lead times for BGA-class FPGAs typically run 8 to 16 weeks from factory. Check real-time inventory on DigiKey or Mouser, or request a quote through XAIPART for verified availability.

What is the lead time for 5CGXBC9A6U19C7N?

Lead time for the 5CGXBC9A6U19C7N is approximately 8-16 weeks from Intel factory order for production volumes, with distributor shelf stock sometimes available for prototype orders. Lead times for BGA-packaged FPGAs often extend during allocation periods, so design teams are advised to place non-cancellable, non-returnable orders early when allocating the device to a production BOM.

What is the best drop-in replacement for 5CGXBC9A6U19C7N?

There is no true drop-in replacement for the 5CGXBC9A6U19C7N because the combination of 77K logic elements, 484-ball U19 BGA footprint, and integrated transceivers is unique within the family. Within the Cyclone V GX line, the closest pin-compatible devices are other 5CGXC9-tier variants in the same U19 BGA footprint, such as different speed grades or industrial-temperature siblings; cross-brand equivalents from Lattice or AMD/Xilinx require PCB redesign and are not drop-in.

Can 5CGXBC5C7U19C8N replace 5CGXBC9A6U19C7N?

No, the 5CGXBC5C7U19C8N is not a true drop-in for the 5CGXBC9A6U19C7N. Both share the U19 484-ball BGA footprint, but the 5CGXBC5C7U19C8N belongs to the lower-density 5CGXC5 tier and the speed/temperature designator differs. Pin-by-pin logic-function compatibility cannot be guaranteed because the transceiver and IO complement may vary within the same physical BGA outline.

5CGXBC9A6U19C7N vs 5CGXBC7D7F31C8N - which is better for PCIe applications?

For PCIe Gen2/Gen3 endpoint applications, the 5CGXBC7D7F31C8N (higher 5CGXBC7 tier, larger F31 900-ball BGA package) provides more logic, more transceivers, and more user IOs than the 5CGXBC9A6U19C7N. Choose the 5CGXBC9A6U19C7N when the smaller 484-ball BGA footprint and 77K LEs are sufficient, and choose the 5CGXBC7D7F31C8N when additional logic and IO bandwidth are required.

When should I choose 5CGXBC9A6U19C7N over a Cyclone V E or Cyclone V SE FPGA?

Choose the 5CGXBC9A6U19C7N (Cyclone V GX) over a Cyclone V E or SE part when you need integrated multi-gigabit transceivers and the 77K-LE logic budget is adequate. Cyclone V E lacks transceivers entirely, while Cyclone V SE adds an ARM Cortex-A9 hardcore subsystem. For pure serial-protocol interfacing, the GX tier offers the lowest cost without the hard CPU overhead of SE.

What is the pinout of 5CGXBC9A6U19C7N?

The 5CGXBC9A6U19C7N uses a 484-ball FineLine BGA with a specific ball-map that is documented in the Cyclone V GX family datasheet (the device-specific pin table for the U19 484-FBGA package). Engineers should always refer to the official Intel pin-table file and the Quartus Prime pin-planner for the exact ball assignment, since BGA pin numbering does not follow a simple row/column ordering.

What are the key specifications of 5CGXBC9A6U19C7N that engineers should know?

Engineers designing with the 5CGXBC9A6U19C7N should focus on these key parameters: 77,000 logic elements in the 5CGXC9 tier, 14,251,008 bits of M9K embedded memory (about 4,460 Kbits), 301,000 registers, 6 PLLs, integrated multi-gigabit transceivers, a 1.1 V core supply, the 484-ball U19 FineLine BGA package, and commercial 0°C to +85°C temperature range. The device is fabricated on a TSMC 28 nm low-power process and supported by the Quartus Prime design toolchain.

Is 5CGXBC9A6U19C7N the same as 5CGXBC9C7N?

No, the 5CGXBC9A6U19C7N and 5CGXBC9C7N are not the same part. The full MPN 5CGXBC9A6U19C7N decodes as: 5CGXBC9 = Cyclone V GX, 5CGXC9 tier; A6 = specific die variant/revision; U19 = 484-ball BGA package code; C7 = commercial speed grade 7; N = lead-free. Each segment encodes specific device attributes that distinguish it from any other MPN.

엔지니어링 참조 데이터: 5CGXBC9A6U19C7N — 비교, 설계 지침 및 규정 준수 정보.

선택 가이드

Choose the 5CGXBC9A6U19C7N when your design needs the 5CGXC9 logic tier (77K LEs), integrated multi-gigabit transceivers, and the 484-ball U19 BGA package in a commercial 0°C to +85°C product. For higher logic density, step up to the 5CGXBC7-tier devices (149.5K LEs); for lower density or smaller 5CGXC5-tier designs with the same U19 footprint, the 5CGXBC5C7U19C8N is a drop-in alternative. Industrial deployments should select 'I7' variants rather than 'C7'. Designs requiring larger IO or transceiver counts should choose F27 or F31 packaged parts. The part is supported by the Quartus Prime design toolchain.

대체품과의 비교

파라미터	이 제품	5CGXBC7C7U19C8N	5CGXBC7C6U19C7N	5CGXBC5C7U19C8N	5CGXBC5C7F27C8N	5CGTFD9A5U19A7N
Brand	Intel	Intel	Intel	Intel	Intel	Intel
Package	484-FBGA (U19)	484-FBGA (U19) - same	484-FBGA (U19) - same	484-FBGA (U19) - same	672-FBGA (F27) - differs	484-FBGA (U19) - same
Logic Elements	77000	149500	149500	85000 (approx, 5CGXC5 tier)	85000 (approx, 5CGXC5 tier)	301000 LEs (Cyclone V GT 5CGTFD9 tier)
Embedded Memory	14,251,008 bits	27,440,640 bits (5CGXBC7 tier)	27,440,640 bits	varies by tier; smaller than 5CGXBC9	varies by tier	approximately 19,753,472 bits (5CGTFD9 tier)
Speed Grade	C7 (commercial)	C8 (industrial)	C7 (commercial) - matches	C8 (industrial)	C8 (industrial)	A7 (automotive)
PLLs	6	7	7	6	6	8 (Cyclone V GT)
Transceivers	Integrated (per U19 484-BGA)	Integrated (more channels in F31 package)	Integrated	Integrated	Integrated	Integrated (Cyclone V GT)
Operating Temperature	0°C to +85°C (commercial)	-40°C to +100°C (industrial)	0°C to +85°C (commercial) - matches	-40°C to +100°C (industrial)	-40°C to +100°C (industrial)	-40°C to +125°C (automotive)
Family / Tier	Cyclone V GX / 5CGXBC9	Cyclone V GX / 5CGXBC7	Cyclone V GX / 5CGXBC7	Cyclone V GX / 5CGXBC5	Cyclone V GX / 5CGXBC5	Cyclone V GT / 5CGTFD9

주요 차별점

77K-LE 5CGXC9 logic tier with integrated transceivers in 484-ball U19 BGA (vs 5CGXBC5C7U19C8N)
U19 484-ball package enables smaller footprint than F27/F31 BGA options (vs 5CGXBC7D7F31C8N)
C7 commercial speed grade balances performance and cost (vs 5CGXBC7C7U19C8N (C8 industrial))

설계 노트

The 484-ball U19 BGA at full transceiver utilization can dissipate 3-5 W, requiring PCB thermal relief via inner ground planes and thermal vias under the exposed pad. Estimated: with 28 nm Cyclone V GX static current of approximately 1-2 W plus dynamic power scaling with toggle rate, designers should simulate with the Quartus Prime PowerPlay tool and budget thermal headroom for commercial 0°C to +85°C ambient operation. For industrial deployments, select the 'I7' industrial variant instead of the 'C7' commercial speed/temperature designator.

BGA breakout routing on the 484-ball U19 package requires a high-layer-count PCB (typically 8+ layers with HDI micro-vias). The transceiver balls must be routed with 100 Ω differential impedance to the edge connector or external PHY; signal-integrity simulation is recommended for data rates above 1 Gbps. Decoupling capacitors should be placed as close as possible to each VCC/VCCAUX/GND ball pair, following the Intel Cyclone V GX device pin-table's recommended decoupling scheme.

Do not assume 5CGXC5-tier or 5CGXBC7-tier MPNs share a pin-for-pin ball map with 5CGXBC9-tier devices even when the package code (U19) matches - transceiver channel count and IO bank assignments differ between logic-density tiers. Always run the design through Quartus Prime pin-planner with the target device's exact MPN before tape-out. Also verify configuration mode (MSEL) strapping against the desired configuration scheme (AS, PS, JTAG, or FPP) per the Cyclone V GX configuration handbook.

규정 준수 정보

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Qualified

무연

Yes

무할로겐

Unknown

분쟁 광물

Compliant

RoHS compliance and lead-free N suffix per Altera/Intel product page. Halogen-free status not explicitly stated in verified data. Not AEC-Q100 qualified - choose A7 automotive-tier MPNs (e.g. 5CGTFD9A5U19A7N) for automotive.

데이터 검증일: 2026-09-05 — XAIPART 부품 엔지니어링 팀이 검증하고 관리한 데이터

출처: Distributor, Octopart, Distributor, Manufacturer Product Page, Octopart