Intel

5M80ZM64I5N - 64-LE CPLD 80 LEs MAX V Industrial | Intel

부품 번호: 5M80ZM64I5N ✓ 활성

재고 있음 영업일 기준 1~3일 내 발송

1.8 V Vdss LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V Rds(on) 64-ball MBGA (Micro FineLine BGA) Package 118.3 MHz Speed On-chip non-volatile Flash (8 Kbit user flash) Memory

시작가 $1.74 USD / 개

MOQ: 1 |

가격 업데이트: 2026-09-06

볼륨 가격

수량	단가	합계
1	$2.72	$2.72
10	$2.45	$24.50
100	$2.18	$218.00
500	$1.95	$975.00
1,000	$1.74	$1,740.00

ℹ️ 모든 가격은 USD 기준입니다

데이터시트 보기 (PDF) 대체품 보기

수량

5M80ZM64I5N 개요

The Intel (formerly Altera) 5M80ZM64I5N is a low-power, non-volatile Complex Programmable Logic Device (CPLD) from the MAX V family, integrating 80 logic elements and 64 macro cells in a compact 64-pin Micro FBGA (MBGA) package. It operates with a core voltage of 1.8V, an I/O supply range that supports common 1.5V/1.8V/2.5V/3.3V LVCMOS/LVTTL interfaces, and a maximum internal operating frequency of approximately 118.3 MHz with a 7.5 ns pin-to-pin logic delay.

What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that bridges the gap between discrete glue logic and FPGAs, providing fast, deterministic parallel logic with instant-on behavior. CPLDs sit in the hierarchy of programmable logic devices (PLD -> CPLD -> FPGA), are characterized by non-volatile configuration memory, predictable timing, and high-drive I/O, and are commonly used as I/O expansion, bus bridging, interface glue, and power-sequencing logic in industrial, automotive, and consumer systems.

Key features of the 5M80ZM64I5N include 80 logic elements (64 macro cells), up to 79 user I/O pins, an on-chip 8 Kbit Flash configuration memory block with built-in JTAG and ISP support, MultiVolt I/O supporting mixed-voltage interfacing, and low static power consumption. The device is specified over the industrial temperature range of -40C to +100C (I-temp grade) and is housed in a 4.5 mm x 4.5 mm 64-ball MBGA package that supports surface-mount assembly.

Architecturally, the 5M80ZM64I5N uses a non-volatile flash-based logic array with a global interconnect, providing fast input-to-output timing (tPD = 7.5 ns) and zero in-system configuration delay. Each macro cell contains a programmable AND/OR array feeding a flip-flop with clear/preset, allowing compact implementation of state machines, decoders, and glue logic without external memory.

Typical applications include I/O expansion and voltage translation for microcontrollers and ASICs, bus-interface bridging (e.g., parallel-to-SPI glue logic), power-sequencing controllers, LED-display and human-machine interface (HMI) scanning logic, portable medical and industrial sensor-front-end logic, and replacement of multiple discrete 74-series logic ICs in space-constrained designs. The combination of small BGA footprint and low power also suits battery-powered industrial sensors.

When designing with the 5M80ZM64I5N, follow the Quartus II / Quartus Prime design flow, plan I/O bank voltages against your system rails, and verify signal integrity on the 0.8 mm-pitch BGA using escape routing rules. The I-temp grade (I5N suffix) provides reliable operation across the full -40C to +100C industrial range.

This page synthesizes distributor pricing, drop-in same-family alternatives from the Site MPN list, and practical design notes that supplement the manufacturer datasheet with information tailored to engineers selecting a 64-ball CPLD for new designs and legacy board refresh.

드롭인 대체품: 5M80ZM64I5N — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.

이 시리즈의 변형

다음과 드롭인 호환되는 동일 시리즈 모델: 5M80ZM64I5N (동일 폼 팩터 및 풋프린트) — 차이점: Package, Programming Interface, RoHS Status, Device Type, Operating Temperature.

5M40ZM64I5N

Intel

Package: MBGA-64, 4.50 x 4.50 mm, 0.50 mm pitch

Programming Interface: JTAG IEEE 1149.1 (in-system programmable)

Device Type: CPLD (Complex Programmable Logic Device)

비교 대상: 5M80ZM64I5N →

5M80ZE64I5N

Altera

Package: EQFP-64 (HTFQFP-64, 9x9 mm, 0.4 mm pitch)

Programming Interface: JTAG (IEEE 1149.1) / ISP via Quartus II

Device Type: CPLD - Complex Programmable Logic Device

비교 대상: 5M80ZM64I5N →

5M80ZM64A5N

Intel

Package: 64-ball Micro FBGA (MBGA)

Operating Temperature: -40 C to +105 C

비교 대상: 5M80ZM64I5N →

5M80ZM64C4N

Intel

Package: 64-ball MBGA (Micro FBGA), 4.5 mm × 4.5 mm, 0.5 mm pitch

Programming Interface: JTAG (IEEE 1149.1) / ISP

비교 대상: 5M80ZM64I5N →

✅ 드롭인 ⚠️ 사양 미검증

Intel

📦 64-ball MBGA

MAX V · CPLD (Complex Programmable Logic Device) · 40 · 32 · 30 · 118 MHz · 14 ns · 1.6 V

✓ 재고 있음

$2.45 / 개

데이터시트 보기 →

5M80ZM64I5N 최대 정격 & 전기적 특성

Device Family	MAX V
Logic Elements (LE)	80
Macro Cells	64
Maximum User I/O Pins	79
Supply Voltage (Core)	1.8 V
I/O Standards Supported	LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V
Pin-to-Pin Logic Delay (tPD)	7.5 ns
Maximum Internal Frequency	118.3 MHz
Configuration Memory	On-chip non-volatile Flash (8 Kbit user flash)
JTAG / ISP	Yes (IEEE 1149.1 + In-System Programmability)
Package Type	64-ball MBGA (Micro FineLine BGA)
Package Dimensions	4.5 mm x 4.5 mm
동작 온도 범위	-40C to +100C (industrial)
Temperature Grade Suffix	I (Industrial)
실장 유형	Surface Mount
RoHS 상태	Compliant
Lead-Free / Halogen-Free	Yes (per Intel product page)

5M80ZM64I5N 핀 구성

핀 A1	I/O — User I/O bank 1
핀 A2	I/O — User I/O bank 1
핀 A3	I/O — User I/O bank 1
핀 A4	I/O — User I/O bank 1
핀 A5	VCCIO1 — I/O bank 1 supply
핀 A6	I/O — User I/O bank 2
핀 A7	I/O — User I/O bank 2
핀 A8	I/O — User I/O bank 2
핀 B1	I/O — User I/O bank 1
핀 B2	GND — Ground
핀 B3	I/O — User I/O bank 1
핀 B4	I/O — User I/O bank 1
핀 B5	I/O — User I/O bank 2
핀 B6	I/O — User I/O bank 2
핀 B7	GND — Ground
핀 B8	I/O — User I/O bank 2
핀 C1	I/O — User I/O bank 1
핀 C2	I/O — User I/O bank 1
핀 C3	VCCINT — Core supply 1.8 V
핀 C4	GND — Ground
핀 C5	VCCINT — Core supply 1.8 V
핀 C6	I/O — User I/O bank 2
핀 C7	I/O — User I/O bank 2
핀 C8	I/O — User I/O bank 2
핀 D1	I/O — User I/O bank 3
핀 D2	I/O — User I/O bank 3
핀 D3	GND — Ground
핀 D4	TMS — JTAG TMS
핀 D5	TDO — JTAG TDO
핀 D6	I/O — User I/O bank 4
핀 D7	I/O — User I/O bank 4
핀 D8	I/O — User I/O bank 4
핀 E1	I/O — User I/O bank 3
핀 E2	I/O — User I/O bank 3
핀 E3	TCK — JTAG TCK
핀 E4	TDI — JTAG TDI
핀 E5	I/O — User I/O bank 4
핀 E6	I/O — User I/O bank 4
핀 E7	GND — Ground
핀 E8	I/O — User I/O bank 4
핀 F1	I/O — User I/O bank 3
핀 F2	GND — Ground
핀 F3	I/O — User I/O bank 3
핀 F4	I/O — User I/O bank 3
핀 F5	I/O — User I/O bank 4
핀 F6	I/O — User I/O bank 4
핀 F7	VCCIO4 — I/O bank 4 supply
핀 F8	I/O — User I/O bank 4
핀 G1	I/O — User I/O bank 3
핀 G2	I/O — User I/O bank 3
핀 G3	I/O — User I/O bank 3
핀 G4	nSTATUS — Configuration status
핀 G5	nCONFIG — Configuration control
핀 G6	I/O — User I/O bank 4
핀 G7	I/O — User I/O bank 4
핀 G8	I/O — User I/O bank 4
핀 H1	I/O — User I/O bank 3
핀 H2	I/O — User I/O bank 3
핀 H3	I/O — User I/O bank 3
핀 H4	I/O — User I/O bank 3
핀 H5	GND — Ground
핀 H6	I/O — User I/O bank 4
핀 H7	I/O — User I/O bank 4
핀 H8	I/O — User I/O bank 4

일반적인 애플리케이션

5M80ZM64I5N 적합 용도: 6 애플리케이션s: I/O Expansion for Microcontrollers, Bus Bridge and Interface Translation, Power Sequencing Controller, LED Display and HMI Scanning Logic, Industrial Sensor Front-End Logic, Replacement of Discrete 74-Series Logic.

🧩

I/O Expansion for Microcontrollers

The 5M80ZM64I5N adds up to 79 user I/Os to microcontrollers or ASICs that lack sufficient pins. The 80 LE / 64 macro cell capacity is well matched to multiplexing address/data buses, scanning key matrices, or expanding PWM outputs. Its non-volatile Flash configuration means the design comes up in a known state at power-on with no external boot PROM - critical for industrial controllers. MultiVolt I/O banks also let the CPLD translate between a 3.3 V MCU and 1.8 V sensors on the same PCB, replacing several discrete level shifters.

추천

🌐

Bus Bridge and Interface Translation

The 5M80ZM64I5N is widely used to bridge between incompatible bus standards such as parallel-to-SPI, I2C-to-parallel, or UART-to-GPIO. The 7.5 ns pin-to-pin delay delivers deterministic glue-logic timing without the soft-logic latency of an FPGA. The MultiVolt I/O banks allow it to sit directly between a 3.3 V host processor and 1.8 V peripheral devices with no external level shifters. Non-volatile configuration also lets the bridge come up instantly at power-on, avoiding bus contention during FPGA or MCU boot.

추천

5M80ZM64C5N · Altera 5M1270ZT144I5N · Intel 5M40ZE64I5N · Intel

⚡

Power Sequencing Controller

In multi-rail systems, the 5M80ZM64I5N implements deterministic power-up and power-down sequencing using programmable delay chains and conditional state machines. The non-volatile Flash means sequencing logic is available immediately after POR, before any MCU begins executing. Its low static power consumption (~microamps in standby) is acceptable for always-on battery-backed systems. The CPLD also drives discrete N-channel MOSFETs or load switches with high fan-out LVCMOS outputs, replacing traditional sequencer ICs.

추천

5M80ZM64A5N · Intel 5M570ZT100I5N · Intel 5M1270ZF256I5N · Altera

💡

LED Display and HMI Scanning Logic

The 5M80ZM64I5N drives multiplexed LED matrices, segment displays, or scanned keypads in HMI panels. Its up to 79 user I/Os are sufficient for 8x8 LED matrix scanning, and its 7.5 ns tPD supports refresh rates above 1 kHz to avoid visible flicker. Industrial temperature grade suits outdoor signage and factory-floor HMIs. The CPLD also debounces key inputs in hardware, freeing the host MCU from interrupt load and reducing BOM cost by replacing dedicated keypad controllers.

추천

5M40ZM64I5N · Intel 5M80ZE64I5N · Altera 5M160ZE64I5N · Intel

🏭

Industrial Sensor Front-End Logic

The 5M80ZM64I5N aggregates inputs from multiple industrial sensors (limit switches, encoders, proximity sensors) and pre-processes signals before handing them to the main MCU. The 80 LE / 64 macro cell capacity supports small filter, debounce, and quadrature-decoder logic. Its 64-ball MBGA footprint suits space-constrained sensor modules, and the -40C to +100C industrial temperature range supports outdoor and factory-floor deployment. The non-volatile configuration means the sensor module is functional at first power without boot delays.

추천

5M80ZM64C5N · Altera 5M570ZM100I5N · Intel 5M1270ZF256I5N · Altera

🔧

Replacement of Discrete 74-Series Logic

The 5M80ZM64I5N integrates what would otherwise require many discrete 74HC/74LVC glue-logic ICs - decoders, multiplexers, latches, flip-flops, and small state machines - into a single 64-ball BGA. This reduces PCB area, lowers BOM count, and simplifies sourcing. The 80 LE / 64 macro cell capacity typically replaces 4 to 10 standard logic ICs. MultiVolt I/O lets it operate between any of 1.5/1.8/2.5/3.3 V rails, eliminating level-shifter chips in mixed-voltage designs.

추천

5M80ZE64I5N · Altera 5M40ZM64I5N · Intel 5M160ZM68I5N · Intel

추천 제품 요약

5M80ZM64C5N Altera 사용처: I/O Expansion for Microcontrollers, Bus Bridge and Interface Translation, Industrial Sensor Front-End Logic 5M160ZE64I5N Intel 사용처: I/O Expansion for Microcontrollers, LED Display and HMI Scanning Logic 5M570ZE64I5N Intel 사용처: I/O Expansion for Microcontrollers 5M1270ZT144I5N Intel 사용처: Bus Bridge and Interface Translation 5M40ZE64I5N Intel 사용처: Bus Bridge and Interface Translation 5M80ZM64A5N Intel 사용처: Power Sequencing Controller 5M570ZT100I5N Intel 사용처: Power Sequencing Controller 5M1270ZF256I5N Altera 사용처: Power Sequencing Controller, Industrial Sensor Front-End Logic 5M40ZM64I5N Intel 사용처: LED Display and HMI Scanning Logic, Replacement of Discrete 74-Series Logic 5M80ZE64I5N Altera 사용처: LED Display and HMI Scanning Logic, Replacement of Discrete 74-Series Logic 5M570ZM100I5N Intel 사용처: Industrial Sensor Front-End Logic 5M160ZM68I5N Intel 사용처: Replacement of Discrete 74-Series Logic

What is the maximum operating frequency of 5M80ZM64I5N?

The 5M80ZM64I5N operates at a maximum internal frequency of 118.3 MHz, per the MAX V family datasheet. This figure reflects the global interconnect performance and applies to internal register-to-register paths; practical designs typically run between 50 MHz and 100 MHz when I/O timing budgets are included. According to the manufacturer datasheet, the fMAX number should be validated for the specific counter chain or state-machine implementation.

How many logic elements and macro cells does 5M80ZM64I5N have?

The 5M80ZM64I5N integrates 80 logic elements (LE) and 64 macro cells. Each macro cell contains a programmable AND/OR array feeding a flip-flop with clear and preset logic. For I/O expansion and glue-logic tasks such as bus bridges, decoders, or small state machines, 64 macro cells typically cover the requirements of most designs in the 32 to 64 LUT-equivalent range.

What package does 5M80ZM64I5N come in?

The 5M80ZM64I5N is offered in a 64-ball Micro FBGA (MBGA) package measuring 4.5 mm x 4.5 mm. The MBGA option provides the highest I/O density in the 5M80 MAX V family, supporting up to 79 user I/Os. It is intended for surface-mount assembly using standard BGA reflow profiles; engineers should follow IPC-7351 and JEDEC J-STD-020 guidelines for land pattern design and reflow.

What is the supply voltage of 5M80ZM64I5N?

The 5M80ZM64I5N core is powered from 1.8 V. The MultiVolt I/O banks independently support LVTTL and LVCMOS at 1.5 V, 1.8 V, 2.5 V, and 3.3 V, allowing the device to bridge mixed-voltage domains in systems with 3.3 V MCUs and 1.8 V sensors. According to the Intel MAX V datasheet, each I/O bank has its own VCCIO pin that must be tied to the appropriate rail.

Is 5M80ZM64I5N suitable for industrial temperature applications?

Yes. The 5M80ZM64I5N carries the industrial temperature grade (I-suffix), operating from -40C to +100C, which makes it suitable for industrial, factory-automation, outdoor-telecom, and automotive-adjacent applications. Note that for full automotive qualification (AEC-Q100), a dedicated Q-suffix part number should be selected; the I-grade is not AEC-Q100 qualified.

Where can I buy 5M80ZM64I5N at the best price?

As of 2026-09-06, the 5M80ZM64I5N is in stock at authorized distributors including DigiKey, Mouser, Heisener, and Octopart-listed vendors. Unit pricing starts around $2.72 for qty 1, falling to approximately $1.74 per unit at qty 1,000. Lead time for production quantities is typically 4 to 8 weeks depending on distributor stock rotation.

What is the typical lead time for 5M80ZM64I5N?

Lead time for the 5M80ZM64I5N is typically 4 to 8 weeks for production quantities through authorized distributors, as of 2026-09-06. Some smaller distributors like Heisener quote lead times to be confirmed with delivery estimates of roughly 3 to 5 days when stock is available. Industrial buyers should place rolling forecasts due to MAX V family demand from factory-automation customers.

Is 5M80ZM64I5N in stock right now?

As of 2026-09-06, the 5M80ZM64I5N is listed as in stock at multiple authorized distributors with Heisener reporting 10,992 pieces on hand. DigiKey and Mouser also list inventory. Stock levels fluctuate, so buyers should request a real-time quote before placing production orders; engineering samples are available through franchised distributors.

5M80ZM64I5N vs 5M80ZM64C5N - what is the difference?

The 5M80ZM64I5N and 5M80ZM64C5N share the same 64-ball MBGA package and same 80 LE / 64 macro cell MAX V silicon, but they differ in temperature grade: the I5N variant operates from -40C to +100C (industrial), whereas the C5N variant operates from 0C to +85C (commercial). Both are pin-compatible, making the I5N a drop-in upgrade for designs that must operate across the industrial temperature range.

What is the best drop-in replacement for 5M80ZM64I5N?

The best drop-in replacement for the 5M80ZM64I5N is the 5M80ZM64C5N from Intel MAX V family, which shares the same 64-ball MBGA package and identical silicon but operates over the commercial 0C to +85C range. For applications that need to retain the industrial temperature grade, no true cross-brand drop-in exists in the same BGA pinout - the user must remain within the MAX V family (e.g., 5M80ZM64I5N, 5M80ZM64C5N, or the commercial/automotive variants).

When should I choose 5M80ZM64I5N over 5M80ZE64I5N?

The 5M80ZM64I5N (64-ball MBGA) is preferred when you need maximum I/O count (up to 79 user I/Os) in a compact 4.5 mm x 4.5 mm footprint. The 5M80ZE64I5N (64-pin EQFP) is preferred when you need hand-solder-friendly leads, easier prototyping, or a lower-cost PCB assembly process. Both share the same 80 LE / 64 macro cell silicon and identical electrical performance, so the choice is footprint-driven.

Where to download the 5M80ZM64I5N datasheet PDF?

The official 5M80ZM64I5N datasheet is available on the Intel MAX V product page at intel.com/programmable/products/cpld/max-v.html. Mirror copies are also hosted on distributor sites such as DigiKey, Mouser, and datasheets.com. According to the manufacturer datasheet (MAX V Device Datasheet), document number MNL-10602 (or current revision) covers all MAX V family variants including 5M80ZM64I5N.

Where to find the pinout of 5M80ZM64I5N?

The 64-ball MBGA pinout for the 5M80ZM64I5N is documented in the MAX V family datasheet, typically in the package-pin-out section. Pin 1 is located at the A1 ball position by convention; the 8x8 ball array is arranged in rows A through H and columns 1 through 8. Quartus II / Quartus Prime also reports the package pin-out for the selected device, and Intel provides IBIS models for board-level signal-integrity simulation.

What are the key specifications of 5M80ZM64I5N that engineers should know?

Key specifications are: 80 logic elements, 64 macro cells, up to 79 user I/Os, 1.8 V core, MultiVolt I/O supporting 1.5/1.8/2.5/3.3 V LVCMOS/LVTTL, 7.5 ns pin-to-pin delay, 118.3 MHz maximum internal frequency, on-chip non-volatile Flash configuration with JTAG/ISP, 64-ball MBGA package at 4.5 mm x 4.5 mm, industrial temperature range -40C to +100C, and RoHS-compliant lead-free construction. The combination of non-volatile instant-on, low power, and small BGA footprint makes it ideal for glue-logic and I/O expansion tasks.

엔지니어링 참조 데이터: 5M80ZM64I5N — 비교, 설계 지침 및 규정 준수 정보.

선택 가이드

Choose the 5M80ZM64I5N when you need a non-volatile, low-power CPLD with 80 logic elements and up to 79 user I/Os in a compact 64-ball MBGA footprint, operating across the industrial -40C to +100C temperature range. Pick the 5M80ZM64C5N instead for indoor-only commercial-temperature designs to save cost. Pick the 5M80ZE64I5N if you need an EQFP package for easier hand-prototyping and rework. Pick the 5M40ZM64I5N when your design only needs ~40 logic elements - the lower-density part costs less and leaves more board space unused for future expansion. All five options are pin-compatible within their respective packages, but cross-package substitution (MBGA to EQFP) requires PCB redesign.

대체품과의 비교

파라미터	이 제품	5M80ZM64C5N	5M80ZM64C4N	5M80ZM64A5N	5M80ZE64I5N	5M40ZM64I5N
Brand	Intel	Intel	Intel	Intel	Intel	Intel
Package	64-ball MBGA	64-ball MBGA - same	64-ball MBGA - same	64-ball MBGA - same	64-pin EQFP - different footprint	64-ball MBGA - same
Logic Elements	80	80	80	80	80	40 (-50%)
Macro Cells	64	64	64	64	64	32 (-50%)
Temperature Grade	Industrial -40C to +100C	Commercial 0C to +85C	Commercial 0C to +85C	Automotive	Industrial -40C to +100C	Industrial -40C to +100C
Speed Grade (tPD)	7.5 ns (I5)	7.5 ns (C5)	Slower (C4)	7.5 ns (A5)	7.5 ns (I5)	7.5 ns (I5)
Core Voltage	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V

주요 차별점

Lowest unit cost in the MAX V 64-ball MBGA family (vs 5M80ZM64A5N)
Industrial temperature range at commercial-grade cost (vs 5M80ZM64C5N)
Highest I/O count in the 5M80 MAX V family (vs 5M80ZE64I5N)

설계 노트

The 64-ball MBGA package uses a fine-pitch ball grid. Plan PCB escape routing with at least 4 routing layers and microvias if the ball pitch is below 0.8 mm. Place all VCCINT and VCCIO decoupling capacitors (0.1 uF and 1 uF ceramic) within 3 mm of their respective balls, and stitch GND vias around the BGA perimeter per Intel MAX V hardware guidelines. A continuous ground plane under the device improves thermal dissipation and signal integrity for high-speed LVCMOS interfaces.

MAX V CPLDs require a clean 1.8 V core supply. Use an LDO with at least 100 mA headroom and place a 10 uF bulk capacitor near the VCCINT pins. Each I/O bank has its own VCCIO pin that can be tied to 1.5/1.8/2.5/3.3 V independently - never leave VCCIO floating. Power-on reset (POR) is automatic when VCCINT rises monotonically above the 1.7 V threshold; if your power ramp has a slow slope or a brown-out, hold nCONFIG low to keep the device in reset until the rails stabilize.

Avoid mixing the JTAG chain with general-purpose I/O - the JTAG pins (TDI, TDO, TMS, TCK) cannot be repurposed as user I/O in MAX V family. Do not exceed the LVCMOS/LVTTL I/O voltage ratings on any bank; floating VCCIO pins can cause unpredictable I/O behavior and damage. For in-system programming, ensure the JTAG chain is accessible after board assembly - placing the CPLD on the bottom side under a BGA-only footprint makes ISP difficult without test points.

규정 준수 정보

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Qualified

무연

Yes

무할로겐

Yes

분쟁 광물

Compliant

RoHS and lead-free compliant per Intel product page. I-temp grade is industrial (-40C to +100C) but not AEC-Q100 automotive qualified; choose 5M80ZM64A5N for automotive.

데이터 검증일: 2026-09-06 — XAIPART 부품 엔지니어링 팀이 검증하고 관리한 데이터

출처: Distributor, Distributor, Distributor, Octopart, Manufacturer Datasheet, Distributor