ADC1001CCJ - 10-Bit µP Compatible SAR ADC, 20-CDIP | Texas Instruments
부품 번호: ADC1001CCJ ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.6 | $4,300.00 |
| 1,000 | $7.45 | $7,450.00 |
ADC1001CCJ 개요
An SAR (Successive Approximation Register) ADC is a class of data converter that uses a binary search algorithm and an internal DAC to converge on the input voltage one bit per clock cycle. SAR ADCs occupy the middle of the converter hierarchy between flash converters (fastest, lowest resolution) and sigma-delta converters (slowest, highest resolution), offering a favorable trade-off of speed, accuracy, and simplicity. The ADC1001 specifically is pin-compatible with the legacy ADC0801 8-bit family, allowing direct 10-bit upgrade on existing 8-bit socket boards, and reads its 10-bit result as two 8-bit bytes (left-justified, high byte first) so it can connect to 8-bit microprocessors without external glue logic.
Key features of the ADC1001CCJ include differential analog input with on-chip sample-and-hold, guaranteed no-missing-codes operation, ratiometric or absolute voltage reference input, and TTL/CMOS-compatible digital outputs. The 20-CDIP ceramic package provides 0C to 70C commercial operating range and excellent long-term reliability for legacy through-hole industrial designs.
The device uses a charge-redistribution DAC array combined with a successive-approximation register and comparator to perform the conversion. Conversions are initiated by a falling edge on WR/RDBC (pin 6), and the result is read as two successive bytes from the parallel data bus DB0-DB9. Internal clock generation requires only an external RC network on pins 19 and 4.
Typical applications include process control data acquisition boards, legacy 8-bit microprocessor measurement front-ends, panel-meter and instrumentation digitizers, and battery-cell voltage monitors. The ceramic CDIP package is especially valued in military, aerospace, and high-reliability industrial systems where plastic DIP and SMD alternatives are not accepted.
When designing with this ADC, ensure the analog input does not exceed VREF+0.3V or go below GND-0.3V to avoid latch-up. Decouple VCC (pin 20) with 1uF tantalum in parallel with 0.1uF ceramic placed within 5mm of the supply pin, and provide a clean low-impedance VREF trace to preserve the converter's 10-bit linearity.
This page synthesizes distributor availability, drop-in same-package alternatives, and practical design notes that go beyond the manufacturer datasheet's application section.
드롭인 대체품: ADC1001CCJ — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC1001CCJ-1
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC1001CCJ/NOPB
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC1001CCJ-1/A+
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC1001BIN
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC1005BJ
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADC1001CCJ 최대 정격 & 전기적 특성
| Manufacturer | Texas Instruments (originally National Semiconductor) |
| Number of Bits | 10 |
| Architecture | SAR (Successive Approximation Register) |
| Number of Inputs | 1 (Differential) |
| 샘플링 속도 | 4.6 kSPS |
| Data Interface | Parallel |
| 패키지 | 20-CDIP (0.300 inch, 7.62mm) through-hole, ceramic |
| 핀 수 | 20 |
| 입력 전압 범위 | 0 V to VCC (ratiometric with VREF) |
| 기준 전압 | External, applied to VREF+ pin |
| 동작 온도 | -40C to +85C (industrial) |
| 실장 유형 | Through-Hole |
| Packaging | Tube |
| RoHS 상태 | non_compliant (ceramic DIP, contains lead) |
| Output Format | Parallel, two 8-bit bytes (left-justified, high byte first) |
| Conversion Initiate | WR/RDBC pin (falling edge) |
| Internal Clock | Yes (external RC required on CLK pins 19 and 4) |
ADC1001CCJ 핀 구성
| 핀 1 | VIN+ — Non-inverting analog input |
| 핀 2 | NC — No internal connection |
| 핀 3 | NC — No internal connection |
| 핀 4 | CLK RC — Clock RC network (R to VCC, C to GND) |
| 핀 5 | INTR — Interrupt output (active low when conversion complete) |
| 핀 6 | WR/RDBC — Write / Read-bar-conversion-control (falling edge starts conversion) |
| 핀 7 | RD — Read strobe (active low) |
| 핀 8 | CS — Chip select (active low) |
| 핀 9 | VREF — Voltage reference input (top of conversion range) |
| 핀 10 | DB7 — Data bit 7 (MSB of high byte) |
| 핀 11 | DB6 — Data bit 6 |
| 핀 12 | DB5 — Data bit 5 |
| 핀 13 | DB4 — Data bit 4 (LSB of high byte) |
| 핀 14 | DB3 — Data bit 3 (MSB of low byte, always 0) |
| 핀 15 | DB2 — Data bit 2 (always 0) |
| 핀 16 | DB1 — Data bit 1 (always 0) |
| 핀 17 | DB0 — Data bit 0 (always 0, LSB) |
| 핀 18 | AGND — Analog ground |
| 핀 19 | CLK R — Clock R resistor (R to VCC) |
| 핀 20 | VCC — +5V supply |
일반적인 애플리케이션
ADC1001CCJ 적합 용도: 6 애플리케이션s: Process Control Data Acquisition, Legacy 8-Bit Microprocessor Measurement Front-End, Panel Meter and Instrumentation Digitizer, Battery Cell Voltage Monitoring, Military and Aerospace Avionics Retrofit, Sensor Signal Conditioning Module.
Process Control Data Acquisition
The ADC1001CCJ's 10-bit resolution and 4.6 kSPS throughput suit slow analog process signals (4-20 mA loops, thermocouple amplifiers, pressure transducers) in industrial PLCs and SCADA front-ends. The differential analog input rejects common-mode noise on long sensor runs, and the parallel data bus interfaces directly to legacy 8-bit 8051-family microcontrollers without glue logic. Compared to modern 12-bit SARs the ADC1001CCJ is preferred in this application only when an obsolete 20-CDIP socket already exists; otherwise a 12-bit ADC0848BCN/NOPB is recommended for new builds.
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Legacy 8-Bit Microprocessor Measurement Front-End
The ADC1001CCJ is intentionally designed to plug into ADC0801 8-bit ADC sockets, presenting the 10-bit conversion as two 8-bit bytes that an 8051, Z80, or 68HC11 can read in two bus cycles. This makes it a clean upgrade path for legacy embedded boards needing higher resolution without firmware or PCB changes. The ceramic 20-CDIP package supports industrial temperature boards and high-reliability systems where plastic SMD would not be accepted. For pure 8-bit designs in the same role, ADC0801S040TS/C1 is the modern surface-mount equivalent.
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Panel Meter and Instrumentation Digitizer
The ADC1001CCJ's ratiometric reference input and 4.6 kSPS rate are well matched to panel meters, digital multimeters, and benchtop instrumentation digitizing DC and slowly-varying analog signals. Its 10-bit resolution (1024 codes) gives 0.1% display resolution when paired with a 3.5-digit LCD driver, while the differential input rejects ground-loop noise in industrial test setups. The ceramic CDIP package is preferred in legacy military/aerospace test equipment where hermeticity and traceable supply are mandatory.
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Battery Cell Voltage Monitoring
In battery-management systems for stationary backup banks and 12V/24V lead-acid stacks, the ADC1001CCJ's single-ended 0-VCC input range can digitize individual cell voltages via a resistor divider, and the 4.6 kSPS rate easily keeps up with the slow 1 Hz to 100 Hz update rate of cell monitoring. The 5V supply is conveniently drawn from the same rail being monitored. For new lithium-ion designs requiring higher resolution and multiple channels, AD7280A or ADS1115 are modern equivalents, but for retrofitting legacy 8-bit BMS boards the ADC1001CCJ is a clean drop-in.
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Military and Aerospace Avionics Retrofit
The ceramic 20-CDIP (hermetic) package of the ADC1001CCJ is qualified for legacy MIL-STD-883 and high-reliability avionics programs where plastic-encapsulated ICs are rejected. The wide -40C to +85C operating range and the absence of software/firmware dependencies (pure hardware conversion) suit long-lifecycle defense platforms. Long-term programs are migrating to rad-tolerant modern SARs like the AD7892AR-1, but for sustainment of fielded systems the ADC1001CCJ remains a specified, drop-in part.
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Sensor Signal Conditioning Module
The ADC1001CCJ's differential input, 10-bit resolution, and external VREF input make it a flexible front-end for bridge sensors (strain gauges, load cells) and low-frequency analog sensors. The user applies the bridge excitation as VREF and the bridge output as VIN+/VIN-, so conversion is ratiometric and rejects drift in the excitation source. The 4.6 kSPS rate is sufficient for slow mechanical measurements. For higher-resolution bridge readout, AD7730 or ADS1231 are modern 20+ bit alternatives, but for 8/10-bit systems the ADC1001CCJ is a documented part.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1001CCJ — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1001CCJ-1 | ADC1001CCJ/NOPB | ADC1001CCJ-1/A+ | ADC1001BIN | ADC1005BJ |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments (orig. National Semiconductor) | Texas Instruments | Texas Instruments | National Semiconductor (TI) | Texas Instruments | Texas Instruments |
| Package | 20-CDIP (0.300 inch, 7.62mm) ceramic | 20-CDIP (0.300 inch) - same | 20-CDIP (0.300 inch) - same | 20-CDIP (0.300 inch) - same | 20-PDIP (0.300 inch) - same footprint, plastic | 20-CDIP (0.300 inch) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Architecture | SAR | SAR | SAR | SAR | SAR | SAR |
| Linearity Grade | Standard | Tightened | Standard | Tightened | Standard | Standard |
| RoHS Status | non_compliant (ceramic, lead-bearing) | non_compliant | non_compliant | non_compliant | compliant (plastic) | non_compliant |
주요 차별점
- Only ceramic-CDIP 10-bit SAR ADC with documented ADC0801 socket drop-in compatibility (vs ADC1001BIN)
- Tightened-linearity grade available in the same package (vs ADC1001CCJ-1)
- Industrial temperature grade variant in same 20-CDIP package (vs ADC1001CCJ/NOPB)
설계 노트
Estimated: the ADC1001 draws typically 1.5 mA quiescent current at 5V per the datasheet family. Decouple VCC (pin 20) with 1uF tantalum in parallel with 0.1uF ceramic placed within 5mm of the pin. Use a star-ground topology tying AGND (pin 18) directly to the system analog ground plane; do not share the digital-return path with analog signal return to avoid code-dependent switching noise coupling into the comparator reference. [DATA_NEEDED: exact quiescent current spec]
Do not allow VIN+ to exceed VCC+0.3V or fall below GND-0.3V - the input ESD structure will forward-bias and inject substrate currents that corrupt ongoing conversions. Always define the analog input range with VREF such that the maximum expected input equals VREF, never VCC. Avoid long VIN+ traces (>25mm) without a guard trace tied to VREF or analog ground to keep digital switching noise from coupling into the comparator.
Route the parallel data bus DB0-DB7 (pins 10-17) as a tightly-coupled bus and keep it away from VIN+ and VREF. The WR/RDBC (pin 6) and RD (pin 7) strobe lines should be short and never run parallel to analog traces. Place the CLK RC network (pin 4) and CLK R resistor (pin 19) on the same PCB side as the IC, with the capacitor returned to pin 18 (AGND) directly, not to a remote ground.
규정 준수 정보
Ceramic 20-CDIP package contains lead-bearing solder/terminations and is non-RoHS. REACH compliance per TI product environmental statements. Not AEC-Q100 qualified (industrial/military grade, not automotive).
