ADC1012D080HN/C1 - 10-bit Dual 80MSPS ADC, LVDS, HVQFN-64 | NXP
부품 번호: ADC1012D080HN/C1 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.85 | $348.50 |
| 100 | $30.2 | $3,020.00 |
| 500 | $26.95 | $13,475.00 |
| 1,000 | $23.4 | $23,400.00 |
ADC1012D080HN/C1 개요
An analog-to-digital converter (ADC) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes, enabling microprocessors, FPGAs, and DSPs to process real-world phenomena such as RF, audio, video, vibration, and sensor measurements. ADCs sit at the boundary between the analog front-end (amplifiers, filters, mixers) and the digital signal-processing chain. Within the converter family, the ADC1012D080HN/C1 is a pipelined flash-type ADC, which sits in the hierarchy: ADC -> data converter -> data acquisition IC -> signal chain -> mixed-signal semiconductor. Pipelined ADCs use a multi-stage architecture with inter-stage gain and error correction, offering an optimal trade-off between sampling speed (tens of MSPS to hundreds of MSPS) and resolution (8-14 bits).
Key features include selectable single or dual-channel operation, an internal bandgap voltage reference, LVDS outputs with internal termination, a low-jitter differential clock input, and per-channel offset and gain calibration registers. The integrated input buffer and on-chip common-mode voltage generator simplify external front-end design, while individual channel power-down reduces quiescent dissipation to less than 1 mW when only one ADC is needed.
Architecturally, each channel uses 9 pipeline stages with proprietary bit-error-correction, clocked by an internal duty-cycle stabilizer that tolerates non-50% input clocks. The dual ADC cores share the same package substrate and reference, ensuring tight gain and offset matching between channels. This matching, typically within 0.1 dB gain and 2 LSB offset, makes the part especially attractive for I/Q demodulation, diversity receivers, and medical imaging front-ends where channel-to-channel skew must be minimized.
Typical applications include communications receivers (cellular base-station observation receivers, microwave-link IF digitizers), industrial ultrasound beamformers, portable instrumentation, software-defined radio (SDR) front-ends, and multi-channel data-acquisition systems. The dual-channel capability also simplifies time-interleaved high-speed designs and quadrature (I/Q) signal capture.
When designing with the ADC1012D080HN/C1, provide a clean differential clock and tightly-coupled LVDS output routing with controlled 100-ohm differential impedance. Decouple AVDD and DVDD supplies with separate ferrite beads and place 100 nF plus 10 uF ceramic capacitors close to the supply pins; the exposed thermal pad must be soldered to a continuous ground plane for thermal and electrical performance.
드롭인 대체품: ADC1012D080HN/C1 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC1012D080HN/C1 (동일 폼 팩터 및 풋프린트) — 차이점: Number of Channels, Operating Temperature, Package, Resolution, Architecture.
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ADC1010S080HN/C1:5
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$7.32 / 개
데이터시트 보기 →ADC1010S105HN/C1:5
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$9.62 / 개
데이터시트 보기 →ADC1012D080HN/C1:5
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$12.1 / 개
데이터시트 보기 →ADC1012D080HN/C1 최대 정격 & 전기적 특성
| 분해능 | 10 bits |
| Number of Channels | 2 (dual, also single-channel mode) |
| Sampling Rate (per channel) | 80 MSPS |
| Input Type | Differential analog |
| Data Interface | Serial, LVDS |
| Architecture | Pipelined, with internal sample-and-hold |
| 패키지 / 케이스 | 64-VFQFN Exposed Pad (HVQFN-64, 9x9 mm) |
| 실장 유형 | Surface Mount |
| SNR (fIN = 70 MHz) | 61 dBFS (typ) |
| SFDR (fIN = 70 MHz) | 84 dBc (typ) |
| Power-Down Mode | Per-channel |
| Reference | Internal bandgap |
| Clock Input | Differential, LVDS/LVPECL compatible |
| RoHS 상태 | Compliant |
ADC1012D080HN/C1 핀 구성
| 핀 1 | AVDD1 — Analog supply, channel 1 |
| 핀 2 | AVSS1 — Analog ground, channel 1 |
| 핀 3 | INA_P — Differential analog input positive, channel 1 |
| 핀 4 | INA_N — Differential analog input negative, channel 1 |
| 핀 5 | VCM1 — Common-mode voltage output, channel 1 |
| 핀 6 | AVSS1 — Analog ground, channel 1 |
| 핀 7 | AVDD2 — Analog supply, channel 2 |
| 핀 8 | AVSS2 — Analog ground, channel 2 |
| 핀 9 | INB_P — Differential analog input positive, channel 2 |
| 핀 10 | INB_N — Differential analog input negative, channel 2 |
| 핀 11 | VCM2 — Common-mode voltage output, channel 2 |
| 핀 12 | AVSS2 — Analog ground, channel 2 |
| 핀 13 | AVDD_REF — Analog supply, reference |
| 핀 14 | VREF — Voltage reference bypass |
| 핀 15 | AVSS — Analog ground, reference |
| 핀 16 | CLKIN_P — Differential clock input positive |
| 핀 17 | CLKIN_N — Differential clock input negative |
| 핀 18 | AVSS_CLK — Analog ground, clock |
| 핀 19 | DVDD — Digital supply |
| 핀 20 | DVSS — Digital ground |
| 핀 21 | SDOUT — Serial data output |
| 핀 22 | SCLK — Serial interface clock |
| 핀 23 | CS — Chip select (active low) |
| 핀 24 | RESET — Reset input (active low) |
| 핀 25 | PDNA — Power-down channel A |
| 핀 26 | PDNB — Power-down channel B |
| 핀 27 | DVDD — Digital supply |
| 핀 28 | DVSS — Digital ground |
| 핀 29 | DCLK_P — LVDS data clock output positive |
| 핀 30 | DCLK_N — LVDS data clock output negative |
| 핀 31 | DA0_P — LVDS data output A0 positive |
| 핀 32 | DA0_N — LVDS data output A0 negative |
| 핀 33 | DA1_P — LVDS data output A1 positive |
| 핀 34 | DA1_N — LVDS data output A1 negative |
| 핀 35 | DA2_P — LVDS data output A2 positive |
| 핀 36 | DA2_N — LVDS data output A2 negative |
| 핀 37 | DA3_P — LVDS data output A3 positive |
| 핀 38 | DA3_N — LVDS data output A3 negative |
| 핀 39 | DA4_P — LVDS data output A4 positive |
| 핀 40 | DA4_N — LVDS data output A4 negative |
| 핀 41 | DB0_P — LVDS data output B0 positive |
| 핀 42 | DB0_N — LVDS data output B0 negative |
| 핀 43 | DB1_P — LVDS data output B1 positive |
| 핀 44 | DB1_N — LVDS data output B1 negative |
| 핀 45 | DB2_P — LVDS data output B2 positive |
| 핀 46 | DB2_N — LVDS data output B2 negative |
| 핀 47 | DB3_P — LVDS data output B3 positive |
| 핀 48 | DB3_N — LVDS data output B3 negative |
| 핀 49 | DB4_P — LVDS data output B4 positive |
| 핀 50 | DB4_N — LVDS data output B4 negative |
| 핀 51 | OR_P — LVDS out-of-range positive |
| 핀 52 | OR_N — LVDS out-of-range negative |
| 핀 53 | DVDD — Digital supply |
| 핀 54 | DVSS — Digital ground |
| 핀 55 | NC — Not connected (per datasheet) |
| 핀 56 | NC — Not connected (per datasheet) |
| 핀 57 | AVDD3 — Analog supply, auxiliary |
| 핀 58 | AVSS3 — Analog ground, auxiliary |
| 핀 59 | TEST — Test mode (tie low in normal operation) |
| 핀 60 | AVSS3 — Analog ground, auxiliary |
| 핀 61 | AVDD3 — Analog supply, auxiliary |
| 핀 62 | AVSS — Analog ground |
| 핀 63 | AVDD1 — Analog supply, channel 1 |
| 핀 64 | AVSS1 — Analog ground, channel 1 |
일반적인 애플리케이션
ADC1012D080HN/C1 적합 용도: 6 애플리케이션s: Communications Receiver IF Digitiser, Industrial Ultrasound Beamformer, Software-Defined Radio (SDR) Front-End, Multi-Channel Data Acquisition System, Portable Test & Measurement Instrumentation, Radar and Lidar Signal Capture.
Communications Receiver IF Digitiser
The ADC1012D080HN/C1 suits IF-sampling receivers in cellular base-station observation paths and microwave-link front-ends. Its 80 MSPS per channel and 61 dBFS SNR at 70 MHz input comfortably capture the IF band while preserving dynamic range for adjacent-channel rejection. The dual cores digitise the I and Q paths simultaneously with matched gain (within 0.1 dB) and offset (within 2 LSB), simplifying downstream digital demodulation. The LVDS serial output bridges cleanly to FPGAs such as the Kintex-7 or Zynq-7000 used for baseband DSP. Designers typically route each ADC's LVDS pairs as 100-ohm differential microstrips and isolate AVDD/DVDD with separate ferrite beads.
추천
Industrial Ultrasound Beamformer
Medical and industrial ultrasound beamformers benefit from the ADC1012D080HN/C1's matched dual channels and per-channel power-down. With 80 MSPS per core and 10-bit resolution, each channel can digitise a 32-element transducer array at typical 20-40 MHz acoustic frequencies, supporting real-time beam steering and focusing. The internal bandgap reference and on-chip common-mode bias simplify the front-end, reducing component count and BOM cost. Per-channel shutdown drops quiescent dissipation below 1 mW during receive-only intervals, critical for portable cart-based ultrasound systems. Matched-channel gain tracking (within 0.1 dB) preserves image fidelity across the aperture.
추천
Software-Defined Radio (SDR) Front-End
The ADC1012D080HN/C1 is well-matched to SDR front-ends that demand dual matched ADCs for I/Q baseband capture. Its 80 MSPS per channel gives 40 MHz usable I/Q bandwidth, sufficient for many narrowband and low-IF waveforms such as FM, DAB, AIS, LoRa, and amateur-radio digital modes. The 84 dBc SFDR at 70 MHz input preserves signal purity across the spectrum, while LVDS serial outputs minimise pin count and ease FPGA capture at full rate. Designers typically pair the ADC with an RF front-end tuner and a Zynq-7000 or Cyclone-V SoC FPGA that handles both DSP and host-side interface. Pin-compatible family variants (single-channel 80/105 MSPS) allow scaling the same PCB across product tiers.
추천
Multi-Channel Data Acquisition System
For multi-channel data-acquisition (DAQ) systems, the ADC1012D080HN/C1's dual 80 MSPS cores let designers pack two synchronous sample streams into a single 64-pin footprint. This is particularly useful in 4-, 8-, or 16-channel instruments built from a ladder of identical ADC1012D080HN/C1 devices, where the LVDS interface simplifies backplane routing and the internal reference removes one external component per channel. The 61 dBFS SNR supports typical industrial sensor measurement accuracy, and the per-channel power-down feature lets unused cores enter a sub-1 mW standby during low-duty-cycle acquisitions. Layout guidelines in the NXP datasheet emphasise a continuous ground plane under the exposed thermal pad and 100-ohm differential LVDS routing.
추천
Portable Test & Measurement Instrumentation
Portable digitising oscilloscopes, spectrum analysers, and bench-top instrumentation favour the ADC1012D080HN/C1's combination of dual matched channels, LVDS outputs, and small HVQFN-64 footprint. The 80 MSPS per channel rate, paired with 10-bit resolution, covers a wide class of mid-band signal-analysis tasks without consuming excessive board area. The internal bandgap reference eliminates an external reference IC, while per-channel power-down supports battery-friendly operating profiles. The exposed thermal pad allows sustained operation at elevated ambient temperatures in enclosed instrument cases, provided the PCB copper pour is sized per the NXP application note. Common companion parts include low-jitter clock buffers and FPGA-based DSP for FFT and trigger functions.
추천
Radar and Lidar Signal Capture
Automotive and industrial radar / lidar signal-capture chains can leverage the ADC1012D080HN/C1's dual 80 MSPS channels for IF-stage digitisation or for time-interleaved higher-rate sampling. The 84 dBc SFDR at 70 MHz preserves signal fidelity for FMCW and pulsed-radar intermediate frequencies, while the matched I/Q channels enable direct conversion receiver architectures. The LVDS serial interface reduces EMI in safety-critical automotive installations, and the small HVQFN-64 footprint fits dense multi-channel sensor modules. Designers typically pair the ADC with a Spartan-6 or Zynq-7000 device for chirp generation, range-Doppler processing, and CAN/Ethernet transport.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1012D080HN/C1 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1010S080HN/C1:5 | ADC1010S105HN/C1:5 | ADC1012D080HN/C1:5 |
|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | HVQFN-64 (9x9 mm) - exposed pad | HVQFN-64 (9x9 mm) - same | HVQFN-64 (9x9 mm) - same | HVQFN-64 (9x9 mm) - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits |
| Channels | 2 (dual) | 1 (single) | 1 (single) | 2 (dual) |
| Sampling Rate | 80 MSPS per channel | 80 MSPS (single) | 105 MSPS (single, +31%) | 80 MSPS per channel |
| Data Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
| Per-Channel Power-Down | Yes | Yes | Yes | Yes |
| Internal Reference | Yes (bandgap) | Yes | Yes | Yes |
| Pin-Compatible Drop-In | n/a (this is the reference) | Yes (single-channel variant) | Yes (single, higher MSPS) | Yes (identical die, T&R variant) |
주요 차별점
- True dual-channel 80 MSPS in a single 64-pin HVQFN footprint (vs ADC1010S080HN/C1:5)
- Higher per-channel sampling rate than single-channel NXP family variants (vs ADC1010S105HN/C1:5)
- Internal bandgap reference and per-channel power-down (vs External-reference ADC designs)
설계 노트
Route the LVDS data pairs (DCLK_P/N and DA/DB lanes) as 100-ohm differential microstrip or stripline. Keep trace lengths matched within the same channel to within 0.5 mm to avoid skew that corrupts the LVDS eye. Place a continuous ground plane immediately beneath the LVDS traces and stitch ground vias along the route. The exposed thermal pad must be soldered to a continuous ground pour with multiple thermal vias for heat dissipation and electrical reference.
Decouple AVDD and DVDD supplies with separate ferrite beads and a 100 nF plus 10 uF ceramic capacitor network placed within 5 mm of the respective supply pins. Avoid sharing decoupling components between analog and digital domains to prevent digital switching noise from coupling into the analog front-end. Provide a clean, low-noise regulator for AVDD (e.g. an LDO with sub-20 uVrms noise) to preserve SNR; the ADC1012D080HN/C1's 61 dBFS SNR is only realised when supply noise is below the ADC's noise floor.
Do not leave any LVDS output pair floating - unused pairs should be tied off with a 100-ohm differential termination to prevent false triggering. Avoid routing analog input traces near digital LVDS lanes; if crossovers are unavoidable, use a ground-plane shield between layers. The TEST pin must be tied to digital ground in normal operation - leaving it floating can cause the device to enter test modes that disrupt calibration. Also ensure the CLKIN_P/CLKIN_N differential pair has the proper common-mode voltage set externally, as required by the LVDS/LVPECL driver feeding the clock.
규정 준수 정보
RoHS compliance and lead-free finish per NXP product page. AEC-Q100 not applicable - this is a commercial/industrial grade ADC. For automotive radar or other AEC-Q100 applications, contact NXP about qualified variants.
