ADS62P22IRGC25 - Dual 12-Bit 65MSPS ADC | Texas Instruments
부품 번호: ADS62P22IRGC25 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $22.5 | $22.50 |
| 10 | $20.85 | $208.50 |
| 100 | $18.95 | $1,895.00 |
| 500 | $17.1 | $8,550.00 |
| 1,000 | $15.5 | $15,500.00 |
ADS62P22IRGC25 개요
What is a pipeline ADC? A pipeline analog-to-digital converter is a high-speed Nyquist-rate architecture that processes an input sample through a sequence of low-resolution flash or multiplying-DAC stages, each handling a fraction of the overall conversion and yielding one output sample per clock cycle after pipeline latency is filled. Within the broader IC taxonomy it sits alongside successive-approximation (SAR), flash, and sigma-delta converters, occupying the niche where 10-14 bit resolution and tens-to-hundreds of MSPS are required, as in communications, instrumentation, and medical imaging.
Key features include a maximum sample rate of 65 MSPS per channel, integrated digital processing with fine gain correction in 0.05 dB steps, and a coarse 3.5 dB gain stage that lets the user trade dynamic range against SNR. The 12-bit core guarantees no missing codes across the full operating range, and the part shares a footprint and digital interface with TI's pin-compatible 14-bit ADS62P4x family, simplifying upgrades and A/B testing between resolutions.
Architecture-wise, the device uses differential input buffers, on-chip references, and a selectable output mode that lets one PCB layout drive parallel CMOS or DDR LVDS signaling. The 64-pin HVQCCN package exposes analog and digital supplies separately, enabling isolation between noisy digital return currents and sensitive analog ground references for high spurious-free dynamic range (SFDR).
Typical applications include multi-carrier wireless infrastructure receivers, ultrasound beam-former front ends, portable medical imaging data acquisition, and dual-channel IF digitisation in software-defined radios. The device's 95 dB channel-to-channel crosstalk and integrated gain control make it particularly attractive where two matched channels are required without external matching networks.
When designing in this ADC, decouple AVDD and DRVDD separately and place a low-impedance ground return directly under the exposed thermal pad to minimise digital noise coupling into the analog front end. Always verify input common-mode and clock duty cycle against the datasheet specifications to maintain SFDR performance.
드롭인 대체품: ADS62P22IRGC25 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS62P22IRGC25 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Output Interface, Number of Channels, Resolution, Input Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS62P42IRGCR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS62P24IRGCR
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADS62P28IRGCR
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
ADS62P48IRGC25
✅ 드롭인✓ 재고 있음
$49.2 / 개
데이터시트 보기 →ADS6242IRGZR
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$18.25 / 개
데이터시트 보기 →ADS62P22IRGC25 최대 정격 & 전기적 특성
| 분해능 | 12 bit |
| Number of Channels | 2 |
| Sampling Rate (max) | 65 MSPS per channel |
| Architecture | Pipeline |
| Input Type | Differential |
| Data Interface | CMOS / DDR LVDS (selectable) |
| 패키지 | 64-pin VQFN (RGC) 9x9 mm |
| 실장 유형 | Surface Mount |
| 동작 온도 범위 | -40C to +85C (Industrial) |
| Supply Voltage - Analog (AVDD) | 3.3 V (typical) |
| Supply Voltage - Digital (DRVDD) | 1.8 V to 3.3 V (typical) |
| Channel-to-Channel Crosstalk | 95 dB |
| Coarse Gain | 3.5 dB |
| Fine Gain Adjustment | 0.05 dB steps up to 6 dB |
| Digital Processing | Offset correction, fine gain correction |
| RoHS 상태 | Compliant |
| MSL 레벨 | 3 |
ADS62P22IRGC25 핀 구성
| 핀 1 | AINP_A — Analog input positive, channel A |
| 핀 2 | AINN_A — Analog input negative, channel A |
| 핀 3 | VCM_A — Common-mode voltage output, channel A |
| 핀 4 | AVDD — Analog supply voltage |
| 핀 5 | AGND — Analog ground |
| 핀 6 | REF — Reference voltage decoupling |
| 핀 7 | AVDD — Analog supply voltage |
| 핀 8 | AGND — Analog ground |
| 핀 9 | AINP_B — Analog input positive, channel B |
| 핀 10 | AINN_B — Analog input negative, channel B |
| 핀 11 | VCM_B — Common-mode voltage output, channel B |
| 핀 12 | AVDD — Analog supply voltage |
| 핀 13 | AGND — Analog ground |
| 핀 14 | CLK — ADC sample clock input |
| 핀 15 | CLKB — Complementary clock input (optional) |
| 핀 16 | DRVDD — Digital output supply voltage |
| 핀 17 | DRGND — Digital ground |
| 핀 18 | RESET — Hardware reset, active low |
| 핀 19 | CS — Serial interface chip select |
| 핀 20 | SCLK — Serial interface clock |
| 핀 21 | SDATA — Serial interface data |
| 핀 22 | SEN — Serial interface enable |
| 핀 23 | DRVDD — Digital output supply voltage |
| 핀 24 | DRGND — Digital ground |
| 핀 25 | D0_A — Channel A data output bit 0 (LSB) |
| 핀 26 | D1_A — Channel A data output bit 1 |
| 핀 27 | D2_A — Channel A data output bit 2 |
| 핀 28 | D3_A — Channel A data output bit 3 |
| 핀 29 | D4_A — Channel A data output bit 4 |
| 핀 30 | D5_A — Channel A data output bit 5 |
| 핀 31 | D6_A — Channel A data output bit 6 |
| 핀 32 | D7_A — Channel A data output bit 7 |
| 핀 33 | D8_A — Channel A data output bit 8 |
| 핀 34 | D9_A — Channel A data output bit 9 |
| 핀 35 | D10_A — Channel A data output bit 10 |
| 핀 36 | D11_A — Channel A data output bit 11 (MSB) |
| 핀 37 | DRGND — Digital ground |
| 핀 38 | DRVDD — Digital output supply voltage |
| 핀 39 | D0_B — Channel B data output bit 0 (LSB) |
| 핀 40 | D1_B — Channel B data output bit 1 |
| 핀 41 | D2_B — Channel B data output bit 2 |
| 핀 42 | D3_B — Channel B data output bit 3 |
| 핀 43 | D4_B — Channel B data output bit 4 |
| 핀 44 | D5_B — Channel B data output bit 5 |
| 핀 45 | D6_B — Channel B data output bit 6 |
| 핀 46 | D7_B — Channel B data output bit 7 |
| 핀 47 | D8_B — Channel B data output bit 8 |
| 핀 48 | D9_B — Channel B data output bit 9 |
| 핀 49 | D10_B — Channel B data output bit 10 |
| 핀 50 | D11_B — Channel B data output bit 11 (MSB) |
| 핀 51 | DRGND — Digital ground |
| 핀 52 | DRVDD — Digital output supply voltage |
| 핀 53 | DCLKP — DDR LVDS data clock positive (LVDS mode) |
| 핀 54 | DCLKN — DDR LVDS data clock negative (LVDS mode) |
| 핀 55 | FCLKP — DDR LVDS frame clock positive (LVDS mode) |
| 핀 56 | FCLKN — DDR LVDS frame clock negative (LVDS mode) |
| 핀 57 | LCLKP — DDR LVDS bit clock positive (LVDS mode) |
| 핀 58 | LCLKN — DDR LVDS bit clock negative (LVDS mode) |
| 핀 59 | DRVDD — Digital output supply voltage |
| 핀 60 | DRGND — Digital ground |
| 핀 61 | AVDD — Analog supply voltage |
| 핀 62 | AGND — Analog ground |
| 핀 63 | AVDD — Analog supply voltage |
| 핀 64 | AGND — Analog ground |
일반적인 애플리케이션
ADS62P22IRGC25 적합 용도: 6 애플리케이션s: Multi-Carrier Wireless Basestation Receiver, Ultrasound Beam-Former Front End, Portable Medical Imaging Data Acquisition, Software-Defined Radio IF Digitisation, Test and Measurement Instrumentation, Industrial Process Control Data Acquisition.
Multi-Carrier Wireless Basestation Receiver
The ADS62P22IRGC25 fits multi-carrier wireless basestation receivers because of dual matched 12-bit 65 MSPS pipeline cores with 95 dB channel-to-channel crosstalk and integrated 3.5 dB coarse / 0.05 dB fine gain for SFDR/SNR trade-off. Each channel can directly digitise an IF or baseband I/Q pair, allowing the FPGA/ASIC to perform channelisation, decimation, and digital predistortion on multiple carriers simultaneously. Unlike a single-channel ADC that requires two parts and matching networks, the dual integrated channel simplifies PCB layout, reduces component count, and improves channel-to-channel phase coherence critical for beam-forming and MIMO systems.
추천
Ultrasound Beam-Former Front End
In portable and cart-based ultrasound imaging, the ADS62P22IRGC25's dual 65 MSPS channels enable beam-former front-end digitisation where phase-aligned matched channels are critical for image reconstruction. The 12-bit resolution and integrated gain stages (3.5 dB coarse, fine 0.05 dB steps up to 6 dB) allow TGC (time-gain-compensation) adjustment in the digital domain. With 95 dB crosstalk isolation, the dual ADC preserves low-amplitude echo signals in the presence of strong adjacent-channel transmissions. Designers value the VQFN-64 footprint's pin-compatibility with the broader ADS62Pxx family, simplifying prototype iteration between channels-per-board trade-offs.
추천
Portable Medical Imaging Data Acquisition
Portable medical imaging data-acquisition systems benefit from the ADS62P22IRGC25's low power consumption at 65 MSPS, dual matched channels, and selectable CMOS or DDR LVDS outputs that flexibly interface with low-power FPGAs or application processors. The 12-bit pipeline architecture delivers Nyquist-rate sampling for physiological waveform capture, while the integrated digital processing block (offset correction, fine gain) reduces the host DSP's post-processing load. Industrial -40C to +85C temperature range and HVQCCN package suit portable enclosures where thermal management and mechanical reliability matter.
추천
Software-Defined Radio IF Digitisation
In software-defined radio (SDR) platforms, the ADS62P22IRGC25 digitises intermediate-frequency (IF) signals on both I and Q paths simultaneously, eliminating I/Q mismatch that plagues discrete dual-ADC designs. The 12-bit, 65 MSPS per-channel rate allows digitisation of IF signals up to approximately 30 MHz, sufficient for narrow-band and many wide-band communications waveforms. CMOS or DDR LVDS digital outputs simplify interface to modern FPGAs implementing the digital down-conversion and demodulation. The VQFN-64 (RGC) footprint and pin-compatibility with the ADS62P4x 14-bit family allow SDR designers to swap resolution without PCB rework as channel requirements evolve.
추천
Test and Measurement Instrumentation
Automated test equipment (ATE) and bench instruments benefit from the ADS62P22IRGC25's dual matched 65 MSPS channels for sampling oscilloscope and signal-analyzer front ends. The integrated gain control (3.5 dB coarse + fine gain) supports input-range scaling in the digital domain, while the 12-bit resolution and 95 dB channel isolation maintain measurement fidelity across differential probes. Selectable CMOS or DDR LVDS digital output modes allow flexible interface to either legacy parallel buses or high-speed serial LVDS link controllers.
추천
Industrial Process Control Data Acquisition
Industrial process-control and condition-monitoring systems leverage the ADS62P22IRGC25's dual channels to digitise vibration, acoustic, or process signals simultaneously. The 12-bit pipeline ADC at 65 MSPS per channel captures transient events that slower SAR ADCs would miss, while the integrated digital processing simplifies per-channel calibration. The industrial -40C to +85C operating temperature and surface-mount VQFN-64 package suit harsh factory-floor enclosures where reliability and wide input range matter for long-life deployments.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS62P22IRGC25 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS62P42IRGCR | ADS62P24IRGCR | ADS62P28IRGCR | ADS62P48IRGC25 | ADS6242IRGZR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGZ) 9x9 mm - same footprint family |
| Resolution | 12 bit | 14 bit | 12 bit | 12 bit | 14 bit | 12 bit |
| Sampling Rate (max) | 65 MSPS/ch | 65 MSPS/ch | 105 MSPS/ch | 125 MSPS/ch | 65 MSPS/ch | 42 MSPS/ch |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Data Interface | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | Serial LVDS only | CMOS / DDR LVDS | CMOS / DDR LVDS |
| Channel Crosstalk | 95 dB | 95 dB | 85 dB | 85 dB | 95 dB | 85 dB |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
주요 차별점
- Pin-compatible 14-bit upgrade path on same PCB (vs ADS62P42IRGCR)
- Dual matched channels with 95 dB crosstalk (vs Discrete dual-ADC design with two single-channel ADCs)
- Integrated digital gain control (vs ADS6242IRGZR)
설계 노트
Decouple AVDD and DRVDD separately to prevent digital switching noise from coupling into the analog front end. Place a 10 uF bulk capacitor and a 0.1 uF ceramic decoupling cap close to each AVDD pin, and similarly for each DRVDD pin. Reference the analog and digital grounds at a single point under the exposed thermal pad to maintain the 95 dB channel crosstalk specification. Estimated total supply current at 65 MSPS is approximately 130 mA from AVDD plus digital output current depending on output mode (CMOS vs DDR LVDS).
Route the analog differential inputs (AINP_A/AINN_A, AINP_B/AINN_B) as length-matched 100 ohm differential traces, kept short and isolated from the digital output bus and clock lines. The exposed thermal pad of the VQFN-64 (RGC) package must be soldered to a continuous ground plane to meet the datasheet thermal resistance. Place the input common-mode capacitors (VCM_A, VCM_B) directly at the respective pins.
Maintain a 50% duty-cycle clock with low jitter (less than approximately 1 ps RMS) at the CLK input to preserve SNR and SFDR; SNR degrades roughly proportional to log(t_jitter). When using DDR LVDS output mode, route the LVDS pairs (DCLK, FCLK, LCLK and data) as length-matched 100 ohm differential traces, terminated close to the receiver. Confirm input common-mode voltage is within the datasheet-specified range for the chosen input configuration.
Do not exceed the absolute maximum AVDD rating; reverse supply connection will damage the device. When migrating firmware between ADS62P22IRGC25 and pin-compatible ADS62P42 (14-bit), update the serial-interface register configuration because register addresses and defaults differ between resolution grades. Always assert RESET after power-up and before initial configuration, per the datasheet power-up sequence.
규정 준수 정보
RoHS compliant per TI product page. Industrial temperature grade (-40C to +85C). Not AEC-Q100 qualified - choose automotive-graded variant for automotive applications.
