ADS6144IRHBR - 14-Bit 105MSPS Low-Power ADC | Texas Instruments
부품 번호: ADS6144IRHBR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.62 | $256.20 |
| 100 | $22.78 | $2,278.00 |
| 500 | $20.45 | $10,225.00 |
| 1,000 | $18.2 | $18,200.00 |
ADS6144IRHBR 개요
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples a continuous-time analog voltage and quantizes it into a discrete digital code. Pipeline ADCs such as the ADS6144 use a multi-stage switched-capacitor architecture that delivers high sample rates (>100 MSPS) at moderate resolution (10-16 bit) with low latency, making them the workhorse of high-speed data acquisition. The ADS6144 belongs to the broader category of data-conversion ICs within the signal-chain semiconductor taxonomy: pipeline ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor.
Key features of the ADS6144IRHBR include an input bandwidth of approximately 700 MHz, spurious-free dynamic range (SFDR) above 80 dBFS at 70 MHz IF, and an SNR of about 72 dBFS at 9.9 MHz input. Programmable full-scale input range spans 1.0 Vpp to 1.5 Vpp, and the parallel CMOS bus can be configured as 1-Wire or 2-Wire DDR LVDS. The 32-pin QFN package provides a low-inductance ground reference through the exposed pad, which is essential for maintaining noise performance above 100 MSPS.
Typical applications for the ADS6144IRHBR include software-defined radio (SDR) receivers, medical imaging front-ends such as ultrasound beamformers, portable test and measurement instruments, multi-carrier cellular base-station cards, and high-speed CCD imaging digitizers. The low power dissipation makes it attractive for dense multi-channel designs where thermal management is challenging.
When designing with this ADC, place the input network and clock-generation components within 5 mm of the package and provide a solid ground reference beneath the exposed pad. The internal reference mode is sufficient for many applications, but for highest SFDR in multi-carrier scenarios, an external low-noise reference such as the REF5025 improves performance by 5-7 dB.
드롭인 대체품: ADS6144IRHBR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS6144IRHBR (동일 폼 팩터 및 풋프린트) — 차이점: Input Type, Package, Digital Supply Voltage, Resolution, Analog Supply Voltage.
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이 제품에는 사용 가능한 드롭인 대체품이 없습니다.
대체품 요청ADS6144IRHBR 최대 정격 & 전기적 특성
| 분해능 | 14 bit |
| Number of Channels | 1 |
| Sampling Rate (Maximum) | 105 MSPS |
| Architecture | Pipelined |
| Input Type | Differential (analog buffered) |
| Full-Scale Input Range | 1.0 Vpp to 1.5 Vpp (programmable) |
| Output Interface | Parallel CMOS / DDR LVDS (selectable) |
| Output Data Format | Offset Binary, Twos Complement, or Gray Code |
| Reference | Internal or External |
| 동작 온도 범위 | -40 C to +85 C (Industrial) |
| 패키지 | 32-VQFN (RHB) 5x5 mm with exposed thermal pad |
| 실장 유형 | Surface Mount |
| MSL 레벨 | 2 (per JEDEC J-STD-020) |
| RoHS 상태 | Compliant |
| Wake-up / Sleep Mode | Yes (power-down pin) |
ADS6144IRHBR 핀 구성
| 핀 1 | AVDD — Analog supply (3.3 V) |
| 핀 2 | INP — Differential analog input positive |
| 핀 3 | INN — Differential analog input negative |
| 핀 4 | AGND — Analog ground |
| 핀 5 | VCM — Common-mode voltage output |
| 핀 6 | AVDD — Analog supply (3.3 V) |
| 핀 7 | REF — Reference voltage bypass |
| 핀 8 | REFT — Reference top decoupling |
| 핀 9 | REFB — Reference bottom decoupling |
| 핀 10 | AVDD — Analog supply (3.3 V) |
| 핀 11 | AGND — Analog ground |
| 핀 12 | NC — Not connected |
| 핀 13 | CLK — Clock input positive |
| 핀 14 | CLK — Clock input negative |
| 핀 15 | AGND — Analog ground |
| 핀 16 | DRVDD — Digital supply (3.3 V) |
| 핀 17 | GND — Digital ground |
| 핀 18 | D0_D6A — LVDS data out / CMOS D6 shared |
| 핀 19 | D1_D6B — LVDS data out / CMOS D6 shared |
| 핀 20 | D2_D0 — LVDS data out / CMOS D0 |
| 핀 21 | D3_D1 — LVDS data out / CMOS D1 |
| 핀 22 | D4_D2 — LVDS data out / CMOS D2 |
| 핀 23 | D5_D3 — LVDS data out / CMOS D3 |
| 핀 24 | DRVDD — Digital supply (3.3 V) |
| 핀 25 | D7_D4 — LVDS data out / CMOS D4 |
| 핀 26 | D8_D5 — LVDS data out / CMOS D5 |
| 핀 27 | DRVCLK — LVDS / CMOS clock output |
| 핀 28 | DRVDD — Digital supply (3.3 V) |
| 핀 29 | CSEL — CMOS/LVDS mode select |
| 핀 30 | SLEEP — Power-down input (active high) |
| 핀 31 | RESET — Reset input |
| 핀 32 | DRVDD — Digital supply (3.3 V) |
| 핀 EP | PAD — Exposed thermal pad - must be soldered to ground plane |
일반적인 애플리케이션
ADS6144IRHBR 적합 용도: 6 애플리케이션s: Software-Defined Radio (SDR) Receiver, Medical Ultrasound Imaging Front-End, Portable Test & Measurement Instrumentation, Multi-Carrier Cellular Base Station Receiver, High-Speed CCD/CIS Imaging Digitizer, Radar / Lidar Pulse Receiver.
Software-Defined Radio (SDR) Receiver
The ADS6144IRHBR's 105 MSPS sampling rate combined with its >700 MHz analog input bandwidth makes it a strong fit for software-defined radio IF-sampling chains. Digitizing a 70 MHz IF at 105 MSPS places the signal comfortably in the second Nyquist zone, where the converter's SFDR remains above 80 dBFS per the TI datasheet. Designers typically place the ADC downstream of a wideband anti-alias filter; the internal differential input buffer tolerates transformer-coupling from the LNA chain. The CMOS/DDR LVDS output option lets the designer route data over an FPGA Mezzanine Card-style connector (for example, paired with Xilinx XC7A35T-1FTG256C) at full rate without compressing the FPGA's LVDS receivers.
추천
Medical Ultrasound Imaging Front-End
In phased-array ultrasound systems the per-channel ADC directly determines harmonic-imaging dynamic range and Doppler sensitivity. The ADS6144IRHBR's 14-bit resolution and 105 MSPS rate suit mid-frequency probes operating at 5-15 MHz; with TGC amplification and bandpass filtering ahead of the converter the system captures second-harmonic content with above-70-dBFS SNR. Designers typically arrange 32 to 128 channels on a single board; the ADC's low 200-mW dissipation keeps the front-end temperature rise manageable under dense packing. The selectable CMOS/LVDS output lets the system serialize channel data across fewer PCB traces to the FPGA beamformer.
추천
Portable Test & Measurement Instrumentation
Handheld oscilloscopes and logic-analyzer-style digitizers benefit from the ADS6144IRHBR's low power envelope, which extends battery runtime without sacrificing update rate. Sampling at 105 MSPS captures real-time digital and analog waveforms up to 50 MHz fundamental content while keeping the ADC's contribution to system power budget under 250 mW. The compact 32-VQFN (RHB) 5x5 mm footprint fits behind probes in space-constrained front-end modules. Internal reference operation simplifies calibration in field-deployable instruments, while external reference mode supports precision bench units.
추천
Multi-Carrier Cellular Base Station Receiver
Multi-carrier GSM/EDGE and LTE receiver cards aggregate multiple carriers onto a single ADC; the ADS6144IRHBR's 80+ dBFS SFDR at 70 MHz IF provides sufficient spurious-free headroom for four-carrier aggregation at typical IF frequencies. Sampling at 105 MSPS captures a 60 MHz IF block with comfortable margin to Nyquist. The CMOS output mode reduces FPGA pin count versus LVDS when board-to-board cabling is short; the LVDS DDR mode is preferred when routing to a backplane or external Mezzanine Card. Paired with a TI GC5330 or GC5316 digital up/down-converter, designers can implement multi-channel base-station cards with a single ADC per antenna branch.
추천
High-Speed CCD/CIS Imaging Digitizer
Scientific-grade CCD and CMOS image sensors deliver wide-bandwidth analog streams that require high-resolution, high-rate digitizers downstream. The 14-bit resolution and 105 MSPS rate of the ADS6144IRHBR capture 4k line-scan imagers streaming 16-bit-equivalent pixel data at pixel-clock rates up to 100 MHz. The differential analog input simplifies integration with correlated double-sampling circuits; the CMOS output bus can be time-multiplexed across two ADCs to support 14-bit color (RGB) simultaneous sampling. Industrial -40 C to +85 C operation supports outdoor machine-vision installations.
추천
Radar / Lidar Pulse Receiver
Short-range radar and lidar receivers digitize single-pulse returns with high dynamic range; the ADS6144IRHBR's 14-bit dynamic range at 105 MSPS supports pulsed-detection thresholds in the 60-70 dBFS range after coherent integration. Sampling pulses 10-50 ns wide at IF frequencies of 50-100 MHz places the return signal comfortably within the ADC's analog input bandwidth. Multi-pulse averaging done in the FPGA downstream further extends the system dynamic range. The CMOS output mode reduces BOM cost versus LVDS for short intra-board hauls, while industrial temperature grade supports outdoor deployment.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS6144IRHBR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS6144IRHBT | ADS6144IRHBRG4 | ADS6143IRHBR | ADS6145IRHBR | ADS6142IRHBR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-VQFN (RHB) 5x5 mm | 32-VQFN (RHB) - same | 32-VQFN (RHB) - same | 32-VQFN (RHB) - same | 32-VQFN (RHB) - same | 32-VQFN (RHB) - same |
| Sampling Rate | 105 MSPS | 105 MSPS | 105 MSPS | 80 MSPS | 125 MSPS | 65 MSPS |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Interface | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Reel/Packaging Variant | Standard R reel | Small T reel | Pb-free G4 reel | Standard R reel | Standard R reel | Standard R reel |
| Approx Unit Price (qty 100) | $22.78 | Similar ($20-$25) | Similar ($20-$25) | Lower ($18-$22) | Higher ($28-$33) | Lower ($16-$20) |
주요 차별점
- Speed grade flexibility within the same package (vs ADS6143IRHBR (80 MSPS))
- Lowest power at 105 MSPS in the family (vs ADS6145IRHBR (125 MSPS))
- Same pinout as the entire ADS614X family (vs ADS6142IRHBR)
설계 노트
The exposed thermal pad on the 32-VQFN (RHB) package must be soldered directly to a solid continuous ground plane. Use at least 4 thermal vias under the pad to stitch the inner planes; missing or ungrounded thermal pad connections degrade dynamic performance by 10-15 dB and may cause intermittent output timing errors at 105 MSPS per the TI datasheet reference design.
Designers should treat the differential analog inputs and clock as 100-ohm differential transmission lines on the PCB. Place the input transformer or driver within 5 mm of the INP/INN pins to minimize parasitic pickup. The clock path must also be 100-ohm differential; a sine-wave PECL clock fed through an AC-coupling capacitor typically yields best jitter performance (<250 fs RMS) for maximizing SFDR at IF inputs above 70 MHz.
Use separate analog and digital 3.3 V regulators; a ferrite bead between AVDD and DRVDD prevents digital switching noise from coupling into the analog front-end. Decoupling: 0.1 uF ceramic + 10 uF ceramic + bulk tantalum or aluminum-polymer 22 uF on each AVDD pin, repeated per pin. Estimated: at 105 MSPS the converter draws approximately 60 mA from AVDD and 30 mA from DRVDD; designers should budget 250 mW dissipation and verify thermal rise with the 32-QFN theta_JA of approximately 30 C/W.
Avoid routing CMOS digital data lines across analog input traces - coupled digital edges produce spurs at predictable offsets in the ADC's output FFT. Common mistake: omitting the CML/LVDS terminations at the FPGA side; unterminated LVDS pairs reflect energy that shows up as pattern-dependent noise at high input frequencies. Always follow the TI reference design footprint and the FPGA Bank I/O standard reference.
규정 준수 정보
RoHS and REACH compliant per TI product page. Lead-free reflow 260 C peak supported per JEDEC J-STD-020 MSL-2. Industrial -40 C to +85 C operating temperature grade. Not AEC-Q100 qualified - the ADS6144 family targets industrial and commercial systems.
