ADS6143IRHBR - 14-Bit 80MSPS Low-Power ADC | Texas Instruments
부품 번호: ADS6143IRHBR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $29.2 | $292.00 |
| 100 | $26.1 | $2,610.00 |
| 500 | $23.45 | $11,725.00 |
| 1,000 | $20.9 | $20,900.00 |
ADS6143IRHBR 개요
An analog-to-digital converter (ADC) is a semiconductor device that converts continuous-time analog signals into discrete digital codes for processing by DSPs, FPGAs, or microcontrollers. Within the data-converter hierarchy, the ADS6143 is a pipelined successive-approximation hybrid ADC - one of the fastest low-power architectures used for IF sampling, instrumentation, and communications. Pipelined ADCs achieve high sampling rates by cascading low-resolution stages, each producing partial conversions in successive clock cycles, then combining them with digital correction logic to deliver a full 14-bit code per sample.
Key features of the ADS6143IRHBR include 73 dBFS SNR at 70 MHz input (typical), 85 dBc SFDR, 0.0244% integral nonlinearity (INL) error, a 3.3 V analog / 1.8 V digital supply architecture, and user-selectable CMOS or DDR LVDS digital interfaces. An integrated 4-bit programmable gain (0 to 6 dB in 1-dB steps) lets designers trade dynamic range for SNR without external amplifiers. The part supports both internal and external clocking modes for flexible synchronization in multi-channel systems.
Typical applications span wireless communication infrastructure (IF sampling for 3G/4G base stations), portable and battery-powered test equipment, handheld spectrum analyzers, medical ultrasound imaging front-ends, software-defined radio (SDR) receivers, and high-speed CCD/CMOS imaging data acquisition. The selectable CMOS/LVDS interface simplifies connection to either low-cost FPGAs (CMOS) or to high-speed LVDS-capable DSPs/ASICs (DDR LVDS).
When designing with this device, provide solid ground and power planes under the package, place decoupling capacitors within 2 mm of each supply pin, and use controlled-impedance differential routing for analog inputs. The DDR LVDS mode halves the output clock rate compared to parallel LVDS, simplifying PCB layout at the FPGA/ASIC boundary. The 32-pin VQFN exposed pad must be soldered to a continuous ground plane for thermal dissipation.
This page synthesizes distributor pricing, drop-in alternatives from the ADS614x family, and practical layout guidance not consolidated in the manufacturer datasheet.
드롭인 대체품: ADS6143IRHBR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS6143IRHBR (동일 폼 팩터 및 풋프린트) — 차이점: Input Type, Package, Digital Supply Voltage, Operating Temperature Range, Output Interface.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS6144IRHBR
✅ 드롭인✓ 재고 있음
$18.2 / 개
데이터시트 보기 →ADS6145IRHBR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6142IRHBR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6143IRHBT
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6143IRHBRG4
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6143IRHBR 최대 정격 & 전기적 특성
| 분해능 | 14 bit |
| Number of Input Channels | 1 |
| Sampling Rate (max) | 80 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| Digital Output Interface | Parallel CMOS or DDR LVDS (selectable) |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V (LVDS mode) / 3.3 V (CMOS mode) |
| Integral Nonlinearity (INL) | 0.0244% (typ) |
| SNR at 70 MHz Input | 73 dBFS (typ) |
| SFDR | 85 dBc (typ) |
| Programmable Gain | 0 to 6 dB in 1-dB steps (4-bit) |
| 동작 온도 범위 | -40C to +85C (Industrial) |
| 패키지 | 32-pin VQFN (RHB), 5x5 mm with exposed pad |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
ADS6143IRHBR 핀 구성
| 핀 1 | AVDD — Analog supply voltage (3.3 V) |
| 핀 2 | AVSS — Analog ground |
| 핀 3 | INA+ — Differential analog input positive |
| 핀 4 | INA- — Differential analog input negative |
| 핀 5 | VCM — Common-mode voltage output (mid-supply reference) |
| 핀 6 | CLKP — Differential clock input positive |
| 핀 7 | CLKM — Differential clock input negative |
| 핀 8 | SENCE — External resistor connection for internal reference |
| 핀 9 | RESET — Reset pin (active low) |
| 핀 10 | PDN — Power-down pin (active high) |
| 핀 11 | DRVDD — Digital output supply (1.8 V or 3.3 V) |
| 핀 12 | DRVSS — Digital output ground |
| 핀 13 | OUTMODE — Output mode select (CMOS or LVDS) |
| 핀 14 | DFS — Data format select |
| 핀 15 | OE — Output enable (active high) |
| 핀 16 | D0 — Data output bit 0 (LSB) |
| 핀 17 | D1 — Data output bit 1 |
| 핀 18 | D2 — Data output bit 2 |
| 핀 19 | D3 — Data output bit 3 |
| 핀 20 | D4 — Data output bit 4 |
| 핀 21 | D5 — Data output bit 5 |
| 핀 22 | D6 — Data output bit 6 |
| 핀 23 | D7 — Data output bit 7 |
| 핀 24 | D8 — Data output bit 8 |
| 핀 25 | D9 — Data output bit 9 |
| 핀 26 | D10 — Data output bit 10 |
| 핀 27 | D11 — Data output bit 11 |
| 핀 28 | D12 — Data output bit 12 |
| 핀 29 | D13 — Data output bit 13 (MSB) |
| 핀 30 | DVDD — Digital core supply (1.8 V) |
| 핀 31 | DGND — Digital ground |
| 핀 32 | NC — Not connected (per datasheet) |
일반적인 애플리케이션
ADS6143IRHBR 적합 용도: 7 애플리케이션s: Wireless IF Sampling (3G/4G Base Station), Portable Battery-Powered Test Equipment, Medical Ultrasound Imaging Front-End, Software-Defined Radio (SDR) Receivers, CCD/CMOS Image Sensor Data Acquisition, Radar and Lidar Signal Processing, Industrial Process Control Instrumentation.
Wireless IF Sampling (3G/4G Base Station)
The ADS6143IRHBR's 73 dBFS SNR at 70 MHz and 80 MSPS sampling rate make it well-suited for IF sampling in 3G/4G wireless base-station receivers where the analog IF stage typically operates between 70 and 140 MHz. The 1.8 V DDR LVDS output mode simplifies high-speed data transfer to a Virtex-6 or Kintex-7 FPGA with minimal pin count, while the 14-bit resolution provides sufficient dynamic range for multicarrier WCDMA/LTE signals at the baseband output. The integrated 4-bit programmable gain (0-6 dB) lets designers fine-tune the input full-scale to match the front-end LNA output without external attenuators.
추천
Portable Battery-Powered Test Equipment
The ADS6143IRHBR's low-power architecture and 3.3 V analog / 1.8 V digital supplies make it ideal for handheld oscilloscopes, portable spectrum analyzers, and field test instruments where battery life matters. The 32-pin VQFN (5x5 mm) footprint keeps the analog front-end compact, while the selectable CMOS output mode allows direct connection to low-cost microcontrollers without needing an LVDS-capable host processor. Designers can pair the ADC with a low-power FPGA for portable data acquisition where the 80 MSPS rate easily captures 40 MHz analog bandwidth with margin.
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Medical Ultrasound Imaging Front-End
The ADS6143IRHBR is a strong candidate for ultrasound beamforming front-ends in mid-tier medical imaging systems, where 14-bit resolution at 80 MSPS per channel captures the dynamic range needed for harmonic imaging. The differential input architecture rejects common-mode noise from the piezoelectric transducer preamps, and the 73 dBFS SNR at high input frequencies supports accurate echo envelope detection. Multiple ADS6143IRHBRs can be synchronized via shared clock for parallel multi-channel acquisition across the ultrasound probe array.
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Software-Defined Radio (SDR) Receivers
In software-defined radio receivers, the ADS6143IRHBR performs direct IF sampling at 80 MSPS, allowing a wide swath of RF spectrum to be digitized and processed digitally rather than through analog mixing stages. The 85 dBc SFDR ensures weak signals are not masked by large blockers, and the DDR LVDS output mode maintains signal integrity over the long cable runs typical of SDR enclosures. Designers can drop in ADS6144 or ADS6145 variants of the same family for higher-bandwidth SDR receivers (up to 125 MSPS) without changing the PCB layout.
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CCD/CMOS Image Sensor Data Acquisition
The ADS6143IRHBR's 80 MSPS sampling rate and 14-bit resolution suit it for digitizing analog outputs from line-scan CCD sensors or high-speed CMOS image sensors in machine-vision and document-scanning applications. The pipelined architecture delivers zero data latency between samples when operated in single-channel mode, and the selectable CMOS parallel output integrates directly with image-processing ASICs. Differential analog inputs reject common-mode noise from the long sensor cable harness typical of industrial scanning systems.
추천
Radar and Lidar Signal Processing
For short-range automotive radar or industrial lidar receiver front-ends, the ADS6143IRHBR samples the analog IF return signal at 80 MSPS, providing 14-bit dynamic range sufficient to resolve both strong nearby and weak distant targets. The -40C to +85C industrial temperature range supports harsh-environment outdoor deployments, and the 32-pin VQFN package's small 5x5 mm footprint eases integration into compact radar modules. Multiple synchronized ADS6143IRHBR channels support phased-array beamforming in next-generation solid-state radar systems.
추천
Industrial Process Control Instrumentation
The ADS6143IRHBR enables high-speed industrial data acquisition modules for vibration monitoring, motor-control feedback, and process-control instrumentation. The 14-bit resolution at 80 MSPS provides oversampling headroom for digital filtering of transducer signals, while the industrial -40C to +85C rating tolerates factory-floor thermal stress. The differential analog input rejects common-mode noise from the long sensor wiring typical of factory environments, and the CMOS output mode simplifies interface to cost-optimized industrial MCUs.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS6143IRHBR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS6144IRHBR | ADS6145IRHBR | ADS6142IRHBR | ADS6143IRHBT | ADS6143IRHBRG4 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-32 (RHB) 5x5 mm | VQFN-32 (RHB) 5x5 mm - same | VQFN-32 (RHB) 5x5 mm - same | VQFN-32 (RHB) 5x5 mm - same | VQFN-32 (RHB) 5x5 mm - same | VQFN-32 (RHB) 5x5 mm - same |
| Sampling Rate | 80 MSPS | 105 MSPS | 125 MSPS | 65 MSPS | 80 MSPS | 80 MSPS |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Input Channels | 1 differential | 1 differential | 1 differential | 1 differential | 1 differential | 1 differential |
| Output Interface | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS | CMOS or DDR LVDS |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
주요 차별점
- Pin-compatible speed-grade upgrade path within ADS614x family (vs ADS6144IRHBR (105 MSPS) / ADS6145IRHBR (125 MSPS))
- Selectable CMOS or DDR LVDS output on one part number (vs Most competitors lock the output type at ordering (e.g., LVDS-only or CMOS-only ordering codes))
- Integrated 4-bit programmable analog gain (0 to 6 dB) (vs AD9245 and similar competitor 14-bit ADCs without on-chip gain)
설계 노트
The ADS6143IRHBR is highly sensitive to power-supply noise; decouple AVDD, DRVDD, and DVDD with a 0.1 uF X7R ceramic capacitor placed within 2 mm of each supply pin, plus a 10 uF bulk tantalum or ceramic capacitor near the IC. The exposed thermal pad (pin 32 EP) MUST be soldered to a continuous ground plane for both thermal dissipation and signal integrity - vias in the pad stitch the top-side ground to inner ground planes. Route the differential analog inputs (INA+/INA-) with 100 ohm controlled-impedance differential traces, and keep them short and symmetric to preserve 73 dBFS SNR.
Do not leave the SENSE pin floating - tie it to AVDD for internal reference use, or to AVSS to enable external reference mode. An unconnected SENSE pin causes the internal reference to drift and degrades SNR. Also ensure CLKP/CLKM are driven by a low-jitter clock source (RMS jitter < 0.5 ps typical for full 14-bit performance at 80 MSPS); excessive clock jitter reduces SNR proportionally to input frequency.
When using DDR LVDS output mode, route the 14 data bits (D[0:13]) and the DDR clock as a tightly-matched bus with 100 ohm differential impedance. Match trace lengths within 5 ps (about 0.6 mm at FR-4 propagation) to maintain setup/hold margins at the receiving FPGA. The OUTMODE pin selects between CMOS and LVDS - hardwire it to DVDD (LVDS) or DGND (CMOS) before the FPGA begins sampling; toggling it during operation can cause output glitches.
Estimated: at 80 MSPS, 3.3 V analog supply, and 1.8 V digital supply with active LVDS output, the ADS6143IRHBR dissipates approximately 250-300 mW. With the VQFN-32 EP package thermal resistance around 32 C/W on a 4-layer JEDEC test board, junction temperature rise above ambient is approximately 10C. Designers in sealed enclosures without airflow should provide copper thermal relief on the exposed pad and avoid placing heat-generating devices adjacent to the ADC.
규정 준수 정보
RoHS and lead-free compliance inferred from the G4 part variant listed in cross-reference data and the TI product page. AEC-Q100 is not applicable - the industrial -40C to +85C rating covers most non-automotive use cases; for AEC-Q100 qualified ADCs, consult TI's automotive portfolio separately.
