ADS61B23IRHB25 - 12-Bit 80MSPS ADC, Buffered Diff Input | TI
부품 번호: ADS61B23IRHB25 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $11.2 | $11.20 |
| 10 | $10.05 | $100.50 |
| 100 | $8.9 | $890.00 |
| 500 | $7.75 | $3,875.00 |
| 1,000 | $6.8 | $6,800.00 |
ADS61B23IRHB25 개요
An ADC (analog-to-digital converter) is a data-conversion integrated circuit that samples continuous analog signals and produces discrete digital codes at a defined sampling rate. High-speed ADCs sit in the signal chain hierarchy between analog signal conditioning (amplifiers, filters) and digital processing (FPGA, ASIC, DSP), and they determine the achievable dynamic range, SNR, and spurious-free dynamic range (SFDR) of the overall system. The ADS61B23 belongs to the pipelined-architecture sub-family, which is the workhorse of 10- to 16-bit, 10- to 250-MSPS communications, medical-imaging, and test-and-measurement front-ends.
Key features include 80 MSPS maximum sampling rate, 12-bit resolution, buffered differential analog inputs that ease driver and interface design, parallel CMOS digital outputs, and an internal reference. The integrated input buffer eliminates the need for an external high-bandwidth op-amp, simplifying board layout and reducing BOM count in space-constrained designs.
Architecturally, the device uses a multi-stage pipelined converter with on-chip sample-and-hold and digital error correction. The buffered front-end presents a high-impedance differential load to the driving amplifier, allowing flexibility in gain-setting and anti-alias filtering, while the parallel CMOS output bus simplifies direct connection to FPGAs and ASICs without an external deserializer.
Typical applications include wireless communications IF/baseband digitization, medical imaging front-ends (ultrasound, MRI), portable and benchtop test and measurement equipment, radar and lidar intermediate-frequency sampling, and high-speed data acquisition systems. The 32-VQFN package with exposed thermal pad enables compact two-layer or four-layer PCB layouts.
When designing with this device, place the input anti-alias filter and common-mode bias network as close to the analog input pins as possible, and route the parallel CMOS output bus with matched trace lengths to the receiving FPGA. A solid ground plane beneath the exposed pad is critical for thermal dissipation and for reducing digital switching noise coupling into the analog front-end.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes for the ADS61B23IRHB25 that complement the manufacturer datasheet, including thermal, layout, and signal-integrity guidance for first-pass design success.
드롭인 대체품: ADS61B23IRHB25 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS61B23IRHB25 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Input Type, Operating Temperature Range, Resolution, Analog Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS61B23IRHBR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS6129IRGZ25
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$23.1 / 개
데이터시트 보기 →ADS61B29IRGZ25
✅ 드롭인✓ 재고 있음
$17.8 / 개
데이터시트 보기 →ADS61B23IRHB25 최대 정격 & 전기적 특성
| 분해능 | 12 bit |
| Number of Channels | 1 |
| 샘플링 속도 | 80 MSPS |
| Input Type | Differential, Buffered |
| Architecture | Pipelined |
| Output Interface | Parallel CMOS |
| 패키지 | 32-VQFN (RHB), 5x5 mm |
| 동작 온도 범위 | -40C to +85C |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
ADS61B23IRHB25 핀 구성
| 핀 1 | INP — Differential analog input (positive) |
| 핀 2 | INN — Differential analog input (negative) |
| 핀 3 | VCM — Common-mode voltage output |
| 핀 4 | AVDD — Analog supply voltage |
| 핀 5 | AGND — Analog ground |
| 핀 6 | REFT — Reference decoupling top |
| 핀 7 | REFB — Reference decoupling bottom |
| 핀 8 | AGND — Analog ground |
| 핀 9 | CLK+ — Differential clock input (positive) |
| 핀 10 | CLK- — Differential clock input (negative) |
| 핀 11 | AGND — Analog ground |
| 핀 12 | AVDD — Analog supply voltage |
| 핀 13 | AGND — Analog ground |
| 핀 14 | DVDD — Digital supply voltage |
| 핀 15 | DGND — Digital ground |
| 핀 16 | D0 — CMOS output data bit 0 (LSB) |
| 핀 17 | D1 — CMOS output data bit 1 |
| 핀 18 | D2 — CMOS output data bit 2 |
| 핀 19 | D3 — CMOS output data bit 3 |
| 핀 20 | D4 — CMOS output data bit 4 |
| 핀 21 | D5 — CMOS output data bit 5 |
| 핀 22 | D6 — CMOS output data bit 6 |
| 핀 23 | D7 — CMOS output data bit 7 |
| 핀 24 | D8 — CMOS output data bit 8 |
| 핀 25 | D9 — CMOS output data bit 9 |
| 핀 26 | D10 — CMOS output data bit 10 |
| 핀 27 | D11 — CMOS output data bit 11 (MSB) |
| 핀 28 | DRDY — Data ready output clock |
| 핀 29 | OE — Output enable (active low) |
| 핀 30 | PD — Power down control |
| 핀 31 | RESET — Reset input |
| 핀 32 | MODE — Mode select (test/internal register select) |
| 핀 33 | EPAD — Exposed thermal pad - connect to analog ground |
일반적인 애플리케이션
ADS61B23IRHB25 적합 용도: 6 애플리케이션s: Wireless Communications IF Sampling, Medical Imaging Front-End (Ultrasound, MRI), Portable Test and Measurement Equipment, Radar and Lidar Intermediate-Frequency Sampling, High-Speed Data Acquisition Systems, Communications Test Equipment.
Wireless Communications IF Sampling
The ADS61B23IRHB25 is well suited to intermediate-frequency digitization in software-defined radio receivers and base-station front-ends. Its 80 MSPS sampling rate captures 30+ MHz instantaneous bandwidth of IF signals after downconversion, and the buffered differential inputs ease interface with the preceding IF amplifier and anti-alias filter. The 12-bit resolution provides 70+ dB SNR, sufficient for narrowband voice and data channels. Parallel CMOS outputs connect directly to FPGAs handling channelization, decimation, and demodulation. The 32-VQFN package fits behind a connector in compact radio modules where board real estate is constrained.
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Medical Imaging Front-End (Ultrasound, MRI)
The ADS61B23IRHB25 supports channel digitization in portable and mid-tier ultrasound systems and MRI receivers. Its buffered differential inputs accept signals from time-gain-compensated (TGC) amplifiers and low-noise preamps, while the pipelined architecture delivers low-latency conversion essential for real-time beamforming. The 12-bit dynamic range and 80 MSPS throughput handle 30+ MHz transducer bandwidth in harmonic imaging modes. The -40C to +85C industrial temperature range supports bedside cart deployment. Compact 32-VQFN packaging enables dense multi-channel boards (32+ channels) needed for high-element-count ultrasound probes.
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Portable Test and Measurement Equipment
The ADS61B23IRHB25 targets handheld oscilloscopes, spectrum analyzers, and data-acquisition modules. Its 80 MSPS rate supports 30+ MHz input bandwidth (Nyquist/2.5), and 12-bit resolution provides 4,096 quantization levels - enough dynamic range for general-purpose signal analysis. The buffered differential inputs reject common-mode noise picked up in industrial bench environments. Parallel CMOS outputs simplify interface to FPGAs implementing triggering, math, and display rendering. The 32-VQFN 5x5 mm package suits handheld form factors with tight mainboard real estate, while the -40C to +85C range supports field-deployed instrument cases.
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Radar and Lidar Intermediate-Frequency Sampling
The ADS61B23IRHB25 suits IF-sampling channels in short-range automotive radar modules and time-of-flight lidar receivers. Its 80 MSPS rate captures 30+ MHz of IF bandwidth from downconverted FMCW chirps or pulsed-laser return signals, while the 12-bit resolution provides dynamic range needed to detect weak return signals alongside large clutter returns. The buffered differential input rejects common-mode noise from the IF mixer, and the parallel CMOS output bus interfaces directly to FPGA-based range-Doppler processors. The 32-VQFN package with exposed thermal pad supports -40C to +85C automotive and industrial environmental testing.
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High-Speed Data Acquisition Systems
The ADS61B23IRHB25 enables multi-channel 12-bit 80 MSPS data acquisition in industrial inspection, vibration analysis, and process control. Its single-channel pipelined architecture is well suited to multiplexed or parallel multi-board deployments where each board captures one high-bandwidth transducer signal. The buffered differential inputs accept signals from bridge amplifiers, charge amplifiers, and IEPE accelerometers. Parallel CMOS outputs route data to FPGAs implementing FFT, spectral analysis, and threshold detection. The 32-VQFN 5x5 mm package enables 4-8 channel front-end cards in standard CompactPCI or PXI chassis formats.
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Communications Test Equipment
The ADS61B23IRHB25 serves as a key component in benchtop signal analyzers, protocol testers, and cable modulators. Its 80 MSPS throughput captures 30+ MHz instantaneous bandwidth of modulated signals (QAM, OFDM, CDMA), and 12-bit resolution provides 70+ dB dynamic range needed for EVM measurements on modern communications standards. The buffered differential input simplifies interface with the test instrument's variable-gain front-end, and the parallel CMOS outputs connect directly to FPGAs implementing demodulation and bit-error-rate analysis. The 32-VQFN package supports integration into 1U benchtop chassis with constrained thermal envelopes.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS61B23IRHB25 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS61B23IRHBR | ADS6129IRGZ25 | ADS61B29IRGZ25 |
|---|---|---|---|---|
| Package | 32-VQFN (RHB) 5x5 mm | 32-VQFN (RHB) - same | 48-VQFN (RGZ) - different | 48-VQFN (RGZ) - different |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 80 MSPS | 80 MSPS | 250 MSPS | 80 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 |
| Input Type | Differential, Buffered | Differential, Buffered | Differential, Buffered | Differential, Buffered |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel LVDS/CMOS | Parallel LVDS |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| RoHS Status | Compliant | Compliant | Compliant | Compliant |
주요 차별점
- Buffered differential input eliminates external driver amplifier (vs ADS6129IRGZ25)
- Compact 32-VQFN 5x5 mm footprint with 80 MSPS throughput (vs ADS61B29IRGZ25)
- Lowest cost TI 12-bit 80 MSPS ADC in VQFN family (vs ADS62P23IRGC25)
설계 노트
Place the input anti-alias RC network within 5 mm of the INP and INN pins, and keep the analog and digital grounds separated until they tie together at the exposed pad (EPAD) of the 32-VQFN package. A solid ground plane beneath the EPAD is mandatory for both thermal dissipation (EPAD sinks most of the converter's heat) and for preventing digital switching noise from coupling into the analog front-end. Route the parallel CMOS output bus with matched trace lengths to the receiving FPGA to avoid setup/hold violations at 80 MSPS.
The differential clock input (CLK+/CLK-) is the most sensitive signal on the board - route it as a tightly coupled 100-ohm differential pair from the clock source directly to the ADC pins, with no vias or stubs. The buffered analog input presents a high-impedance load, but the ADC's dynamic performance (SNR/SFDR) depends heavily on the analog driver's ability to settle within the 12.5 ns sample window at 80 MSPS. Use a low-noise, low-distortion differential driver (e.g., AD8475 or ADL5562) with bandwidth at least 3x the maximum input frequency.
Do not leave the OE (output enable) pin floating - tie it to logic low for normal operation or to logic high for high-Z output. The PD (power down) pin must be tied to logic low for the ADC to operate; floating this pin may cause intermittent power-up states. Decouple AVDD and DVDD with 0.1 uF ceramic capacitors placed within 3 mm of each supply pin, plus a single 10 uF bulk capacitor per supply rail. The reference pins REFT and REFB require 0.1 uF + 10 uF decoupling for low reference noise floor.
규정 준수 정보
RoHS and REACH compliance per Texas Instruments product page. Not AEC-Q100 qualified - for automotive applications consult TI's Q1-grade portfolio. Halogen-free status not explicitly listed in available data.
