ADS61B23 - 12-Bit 80MSPS ADC with Buffered Inputs | TI
MPN: ADS61B23 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $22.1 | $221.00 |
| 100 | $19.8 | $1,980.00 |
| 500 | $17.5 | $8,750.00 |
| 1,000 | $15.2 | $15,200.00 |
Drop-in alternatives for ADS61B23 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
ADS61B23IRHBT
β Drop-Inπ Reference alternative (not in catalog)
ADS61B23IRHBR
β Drop-Inπ Reference alternative (not in catalog)
ADS61B23 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Sampling Rate | 80 MSPS |
| Input Type | Buffered Differential |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V |
| SNR | 69.5 dBFS |
| SFDR | 84 dBc |
| Power Dissipation | 380 mW |
| Reference Mode | Internal or External |
| Output Interface | LVDS or CMOS |
| Package | 32-VQFN (5x5 mm) |
| Operating Temperature | -40C to +85C |
| Mounting Type | Surface Mount |
ADS61B23 Pin Configuration
| Pin 1 | AVDD β Analog supply voltage (3.3V) |
| Pin 2 | AVSS β Analog ground |
| Pin 3 | INP β Non-inverting analog input |
| Pin 4 | INM β Inverting analog input |
| Pin 5 | AVSS β Analog ground |
| Pin 6 | VCM β Common-mode voltage output |
| Pin 7 | AVDD β Analog supply voltage |
| Pin 8 | CLK β Sampling clock input |
| Pin 9 | CLKB β Complementary clock input |
| Pin 10 | DVDD β Digital supply voltage (1.8V) |
| Pin 11 | DVSS β Digital ground |
| Pin 12 | D0 β Digital output bit 0 (LSB) |
| Pin 13 | D1 β Digital output bit 1 |
| Pin 14 | D2 β Digital output bit 2 |
| Pin 15 | D3 β Digital output bit 3 |
| Pin 16 | D4 β Digital output bit 4 |
| Pin 17 | D5 β Digital output bit 5 |
| Pin 18 | D6 β Digital output bit 6 |
| Pin 19 | D7 β Digital output bit 7 |
| Pin 20 | D8 β Digital output bit 8 |
| Pin 21 | D9 β Digital output bit 9 |
| Pin 22 | D10 β Digital output bit 10 |
| Pin 23 | D11 β Digital output bit 11 (MSB) |
| Pin 24 | DVSS β Digital ground |
| Pin 25 | SDO β Serial data output for configuration |
| Pin 26 | SCLK β Serial clock input |
| Pin 27 | SDENB β Serial data enable (active low) |
| Pin 28 | RESET β Reset input |
| Pin 29 | PDN β Power-down control |
| Pin 30 | SLEEP β Sleep mode control |
| Pin 31 | AVDD β Analog supply voltage |
| Pin 32 | AVSS β Analog ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
ADS61B23 is suitable for 6 applications: Wireless Base Stations, Software-Defined Radio, Medical Ultrasound, Radar Systems, High-Speed Data Acquisition, Communications Receivers.
Wireless Base Stations
The ADS61B23's 80MSPS sampling rate and 69.5 dBFS SNR make it ideal for digitizing IF signals in wireless base stations. Its buffered inputs simplify the front-end, and the low power consumption of 380 mW helps reduce thermal load in dense BTS designs. The device's high SFDR of 84 dBc ensures minimal intermodulation distortion, preserving signal integrity in multi-carrier environments. With LVDS outputs, it can interface directly with FPGAs or DSPs for digital down-conversion.
Recommended
Software-Defined Radio
In SDR systems, the ADS61B23 provides high-speed digitization of wideband RF signals. Its 12-bit resolution and 80MSPS sampling rate enable direct IF sampling, reducing the number of analog mixing stages. The buffered inputs allow direct connection to RF front-ends without additional buffer amplifiers, simplifying the design. The device's low power consumption is advantageous for portable SDR platforms, and its internal reference reduces external component count. The LVDS output interface ensures clean data transfer to FPGAs for real-time processing.
Recommended
Medical Ultrasound
The ADS61B23 is well-suited for medical ultrasound systems where high-speed, high-resolution digitization of echo signals is required. Its 12-bit resolution and 80MSPS sampling rate capture fine details in the received signals, while the buffered inputs simplify the interface to the transducer array. The low power consumption helps manage heat in portable ultrasound devices. The device's high SNR ensures clear images with low noise, and the small VQFN package allows for compact probe designs.
Recommended
Radar Systems
In radar applications, the ADS61B23 digitizes IF signals with high dynamic range, enabling detection of weak targets in the presence of strong clutter. Its 80MSPS sampling rate supports wideband waveforms, and the 69.5 dBFS SNR ensures good sensitivity. The buffered inputs reduce kickback, allowing direct connection to the radar receiver front-end. The device's low power consumption is beneficial for phased-array radar modules, and its small package enables high-density integration.
Recommended
High-Speed Data Acquisition
The ADS61B23 is ideal for high-speed data acquisition systems in test and measurement equipment. Its 12-bit resolution and 80MSPS sampling rate allow accurate digitization of fast transient signals. The buffered inputs simplify the front-end design, and the internal reference reduces external components. The device's low power consumption is advantageous for portable instruments, and the LVDS output interface ensures high-speed data transfer to storage or processing units.
Recommended
Communications Receivers
The ADS61B23 is used in communications receivers for digitizing IF signals with high linearity and low noise. Its 12-bit resolution and 80MSPS sampling rate support wideband communication standards. The buffered inputs reduce the need for external drive amplifiers, simplifying the receiver chain. The device's high SFDR of 84 dBc ensures low intermodulation distortion, which is critical in multi-carrier environments. The low power consumption helps in battery-powered or densely packed receiver designs.
Recommended
Recommended Products Summary
Engineering reference data for ADS61B23 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS61B23IRHBT | ADS61B23IRHBR | ADS62C17IRGCR |
|---|---|---|---|---|
| Package | 32-VQFN (5x5 mm) | 32-VQFN (5x5 mm) | 32-VQFN (5x5 mm) | 64-VQFN (9x9 mm) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bits | 12 bits | 12 bits | 14 bits |
| Sampling Rate | 80 MSPS | 80 MSPS | 80 MSPS | 250 MSPS |
| Input Type | Buffered Differential | Buffered Differential | Buffered Differential | Differential |
| SNR | 69.5 dBFS | 69.5 dBFS | 69.5 dBFS | 74 dBFS |
| Power Dissipation | 380 mW | 380 mW | 380 mW | 1.1 W |
| Output Interface | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS | LVDS |
Key Differentiators
- Buffered analog inputs (vs ADS62C17IRGCR)
- Lower power consumption (vs ADS62C17IRGCR)
- Smaller package (vs ADS62C17IRGCR)
Design Notes
The ADS61B23 requires separate analog (3.3V) and digital (1.8V) supplies. Use low-impedance decoupling capacitors (e.g., 0.1uF and 10uF) close to each supply pin to minimize noise. A ferrite bead on the analog supply can help isolate high-frequency noise from the digital supply.
For optimal performance, maintain a solid ground plane and separate analog and digital ground areas, connecting them at a single point. Keep the analog input traces short and shielded to reduce noise pickup. The VQFN package has an exposed thermal pad that should be soldered to the PCB ground plane for heat dissipation.
Ensure the sampling clock is clean and low-jitter to achieve the specified SNR. Use a dedicated clock buffer and avoid routing the clock near digital output traces. Also, set the input common-mode voltage correctly (typically 1.5V) to avoid clipping and maintain linearity.
Compliance Information
RoHS compliant per TI product page. Not AEC-Q100 qualified.
