ADS62P23IRGC25 - Dual 12-bit 80MSPS ADC, DDR LVDS/CMOS | TI
부품 번호: ADS62P23IRGC25 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $31.2 | $31.20 |
| 10 | $28.1 | $281.00 |
| 100 | $24.95 | $2,495.00 |
| 500 | $21.5 | $10,750.00 |
| 1,000 | $18.85 | $18,850.00 |
ADS62P23IRGC25 개요
An analog-to-digital converter (ADC) is a data-conversion IC that translates a continuous analog input voltage into a discrete digital code at each sampling clock edge. Within the signal chain taxonomy, the ADS62P23 belongs to the pipeline ADC sub-family, which sits between successive-approximation register (SAR) ADCs (low speed, low power) and flash ADCs (very high speed, high power). Pipeline ADCs dominate the 10-250 MSPS speed range because they multiplex many low-resolution stages behind a high-speed input, delivering high sample rates with moderate power budgets and small footprints. The ADS62P2X family specifically targets wideband communications, IF-sampling radios, and multi-channel industrial imaging.
Key features include 80 MSPS guaranteed sample rate, 12-bit resolution across two simultaneously-sampled channels (2x2 channel matrix is supported via the family), and a wide analog input bandwidth of approximately 450 MHz. The integrated DDR LVDS interface delivers two data bits per clock cycle on each LVDS pair, halving the required FPGA pin count compared to parallel CMOS. Typical uses cover test and measurement digitizers, communications base-station receivers, medical ultrasound beamformers, and defense signal-intelligence capture cards. Industrial-grade -40C to +85C operation ensures deployment in uncontrolled enclosures. When designing with the device, prioritize short, matched-length traces between the analog inputs and the ADC; place the analog input RC network as close to the analog input pins as the layout allows to preserve SNR/SFDR. The combination of integrated references, selectable output interface, and the 9x9 mm VQFN footprint simplifies board layout versus older ADCs that required external references and LVDS buffers. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes that go beyond the manufacturer datasheet.
드롭인 대체품: ADS62P23IRGC25 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS62P23IRGC25 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Input Type, Resolution, Number of Channels, Analog Supply Voltage.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS62P22IRGC25
✅ 드롭인✓ 재고 있음
$15.5 / 개
데이터시트 보기 →ADS62P24IRGC25
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS62P25IRGC25
✅ 드롭인✓ 재고 있음
$32.5 / 개
데이터시트 보기 →ADS62P23IRGCR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS62P23IRGCT
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS62P44IRGC25
✅ 드롭인✓ 재고 있음
$22.1 / 개
데이터시트 보기 →ADS62P23IRGC25 최대 정격 & 전기적 특성
| Manufacturer | Texas Instruments |
| 분해능 | 12 bit |
| Number of Channels | 2 (dual) |
| Sampling Rate (Max) | 80 MSPS |
| Architecture | Pipelined |
| Output Interface | DDR LVDS or Parallel CMOS (selectable) |
| Input Type | Differential analog inputs |
| Max Analog Input Voltage | 2 V |
| 패키지 | 64-VQFN (RGC) 9x9 mm |
| 실장 유형 | Surface Mount |
| 동작 온도 범위 | -40C to +85C (industrial) |
| Internal Reference | Yes (external reference also supported) |
| Family Member Context | ADS62P2X family (65/80/105/125 MSPS versions) |
| RoHS 상태 | Compliant |
| MSL 레벨 | 3 (168 hours) |
| Product Family | ADS62P2X |
ADS62P23IRGC25 64-vqfn (rgc) 9x9 mm 핀 구성 가이드
ADS62P23IRGC25(64-vqfn (rgc) 9x9 mm 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: ADS62P23IRGC25.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
ADS62P23IRGC25 적합 용도: 6 애플리케이션s: Wideband Communications Receivers, Medical Ultrasound Beamforming, Test and Measurement Digitizers, Industrial Imaging and Machine Vision, Defense Signal Intelligence Capture, Multi-Channel Data Acquisition Cards.
Wideband Communications Receivers
The ADS62P23IRGC25 is well suited to IF-sampling receivers in software-defined radio and LTE base-station front-ends. The dual 12-bit 80 MSPS channels let designers digitize two diversity or two-stage IF paths simultaneously. Per the TI ADS62P2X datasheet, the analog input bandwidth exceeds 450 MHz, comfortably supporting IF frequencies up to 150 MHz without aliasing. The selectable DDR LVDS output reduces FPGA pin count, allowing lower-cost FPGAs to capture both channels. The integrated reference removes external reference noise, and the 9x9 mm VQFN keeps board density high.
추천
Medical Ultrasound Beamforming
The ADS62P23IRGC25 is widely deployed in portable and cart-based ultrasound imaging systems. Each ADC channel digitizes a beamformed or pre-beamformed transducer signal at 12-bit resolution and 80 MSPS, providing adequate dynamic range for tissue harmonics. The TI ADS62P2X datasheet confirms low noise floor and high spurious-free dynamic range (SFDR) required for clean B-mode imaging. Two simultaneously-sampled channels per IC reduce board area and bill of material. The -40C to +85C industrial temperature grade covers portable-cart enclosures, and VQFN-64 footprint simplifies dense multi-channel array layouts.
추천
Test and Measurement Digitizers
The ADS62P23IRGC25 serves as a front-end digitizer in bench oscilloscopes, spectrum analyzers, and modular instrumentation. The 12-bit resolution at 80 MSPS captures transient and repetitive signals with enough vertical resolution for production-line test. Per the TI datasheet, the pipelined architecture combined with selectable DDR LVDS outputs simplifies routing on multi-channel digitizer boards. Engineers use the device to digitize signals up to 40 MHz bandwidth directly, or to capture higher frequencies via an external track-and-hold amplifier. The 9x9 mm VQFN keeps density high.
추천
Industrial Imaging and Machine Vision
The ADS62P23IRGC25 fits dual-channel line-scan camera digitizers and multi-spectral industrial inspection systems. Per the TI ADS62P2X datasheet, the two simultaneous sample-and-hold stages capture synchronized image data from two sensor paths without phase mismatch. The 12-bit dynamic range handles typical line-scan illumination variances, while 80 MSPS comfortably exceeds line rates of even 25 kHz line-scan cameras with adequate oversampling. The industrial -40C to +85C rating supports factory-floor deployment, and the VQFN-64 footprint enables compact camera-head electronics.
추천
Defense Signal Intelligence Capture
The ADS62P23IRGC25 is used in portable and rack-mounted signals-intelligence (SIGINT) capture cards where wide bandwidth and channel density matter. Two simultaneous 80 MSPS 12-bit channels let designers pack more digitizer channels per board than single-channel ADCs. The TI ADS62P2X family datasheet documents low SFDR needed to separate weak signals from strong adjacent ones. The DDR LVDS output mode keeps FPGA pin usage manageable in dense multi-board backplanes. The 9x9 mm VQFN-64 footprint is well suited to VPX and similar small-form-factor cards.
추천
Multi-Channel Data Acquisition Cards
The ADS62P23IRGC25 enables compact, multi-channel DAQ boards for industrial process monitoring and vibration analysis. Each IC provides two simultaneous 12-bit 80 MSPS channels, so a 4-layer board with 8 ICs yields 16 channels. Per the TI ADS62P2X datasheet, the integrated reference and selectable CMOS output mode simplify routing on FPGA-based DAQ controllers. The -40C to +85C industrial temperature grade suits factory and outdoor cabinets. Engineers favor the VQFN-64 footprint for hand-rework access to the perimeter pins during prototyping.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS62P23IRGC25 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS62P22IRGC25 | ADS62P24IRGC25 | ADS62P25IRGC25 | ADS62P44IRGC25 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit |
| Sample Rate | 80 MSPS | 65 MSPS (-19%) | 105 MSPS (+31%) | 125 MSPS (+56%) | 105 MSPS (+31%) |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Output Interface | DDR LVDS or CMOS | DDR LVDS or CMOS | DDR LVDS or CMOS | DDR LVDS or CMOS | DDR LVDS or CMOS |
| Internal Reference | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Family Grade Tier | Mid (80 MSPS) | Low (65 MSPS) | High (105 MSPS) | Top (125 MSPS) | Higher-resolution 14-bit tier |
주요 차별점
- Mid-tier speed in a fully pin-compatible ADS62P2X family (vs ADS62P25IRGC25 (125 MSPS))
- DDR LVDS output mode halves FPGA pin count (vs ADS62P23IRGCT (CMOS-only variant))
- Integrated references reduce external component count (vs ADS62P44IRGC25 (14-bit))
- Dual simultaneous sampling eliminates phase mismatch (vs Single-channel 12-bit 80 MSPS ADCs)
설계 노트
The ADS62P23IRGC25 analog input pins are highly susceptible to noise pickup. Place the analog input RC network (typically 25 ohm series resistor plus 10 pF shunt to ground) within 2-3 mm of the analog input pins per the TI ADS62P2X datasheet. Use a solid ground plane under the analog input traces and avoid routing digital output traces directly under the analog input section to preserve SNR and SFDR.
The ADS62P23IRGC25 requires separate analog and digital supply rails (typically AVDD 3.3 V and DRVDD 1.8 V or 3.3 V). Per the TI datasheet, decouple each supply pin with a 0.1 uF ceramic capacitor in parallel with a 10 uF bulk capacitor placed as close as possible to the pin. Use ferrite beads or pi filters to isolate noisy digital return currents from sensitive analog return currents, and tie the ground planes together at a single point near the IC.
For DDR LVDS output mode, the ADS62P23IRGC25 produces edge rates around 200 ps. Per the TI ADS62P2X datasheet, route the LVDS pairs as 100 ohm differential microstrip with matched lengths within 1 mm to preserve data-eye margins at the FPGA. Avoid via stubs on the LVDS pairs and use ground-plane reference on an adjacent layer. If using CMOS mode, length-match the parallel data bus within one clock period.
The 64-VQFN (RGC) 9x9 mm package dissipates approximately 350 mW per channel at 80 MSPS. Estimated: at 25C ambient with a standard JEDEC 4-layer test board, theta_JA is around 25 C/W, yielding a junction temperature rise of roughly 17.5C above ambient. Solder the exposed thermal pad to a continuous ground-copper pour to achieve this thermal performance; do not let the pad float or junction temperature will rise sharply.
Do not swap the ADS62P23IRGC25 for the ADS62P25IRGC25 (125 MSPS) without re-validating downstream FPGA timing margins. Although pin-compatible, the higher sample rate tightens setup/hold windows and may require FPGA timing adjustments. Also verify the output-mode select pin state at power-up - mixing DDR LVDS with the wrong FPGA receiver block can cause persistent data errors.
규정 준수 정보
RoHS compliant per TI product page. Industrial -40C to +85C temperature grade; not AEC-Q100 automotive qualified. Halogen-free status not explicitly stated in provided data.
