ADC1012D125HN/C1:5 - 10-Bit 125MSPS Dual ADC, HVQFN-64 | NXP
부품 번호: ADC1012D125HN/C1:5 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $21.4 | $21,400.00 |
ADC1012D125HN/C1:5 개요
An ADC (Analog-to-Digital Converter) is a data-acquisition integrated circuit that samples continuous analog signals and produces discrete digital codes at a defined sample rate. Within the broader IC taxonomy, ADCs belong to data converters, which sit inside signal-chain ICs, a category of mixed-signal devices that bridge analog transducers and digital processors. Pipelined ADCs such as the ADC1012D125HN/C1:5 use a cascade of low-resolution stages with digital error correction to achieve high sample rates at moderate resolution.
Key specifications include 10-bit resolution, 125 MSPS maximum sample rate per channel, dual simultaneous-sampling channels, low-voltage differential signaling (LVDS) compatible digital outputs, and an internal reference. The converter operates from a single 3.3 V analog supply and a separate 3.3 V or 1.8 V digital supply, providing isolation between sensitive analog sampling circuits and noisy digital outputs. Typical power dissipation is in the range of several hundred milliwatts.
The pipelined architecture, combined with foreground calibration of the internal MDAC stages, delivers excellent dynamic linearity (typical DNL around ±0.3 LSB) and low spurious content, suitable for communications receivers, radar signal processing, and medical imaging front-ends. Integrated input buffers simplify the interface to driving amplifiers and reduce the need for external anti-alias filtering.
Typical applications include cellular base-station receivers, software-defined radio (SDR) platforms, medical ultrasound beamformers, and high-speed instrumentation. The dual-channel configuration is particularly useful for I/Q demodulation, diversity reception, and direct-IF sampling where matched channels are required.
When designing with this part, route analog and digital grounds as separate planes joined only at the exposed pad, and place 0.1 µF ceramic decoupling capacitors as close as possible to each supply pin. Source-impedance matching at the analog inputs is critical for SFDR performance.
This page combines the manufacturer datasheet, distributor pricing tiers, and verified drop-in alternatives to give engineers a single reference for evaluation and second-source qualification.
드롭인 대체품: ADC1012D125HN/C1:5 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC1012D125HN/C1:5 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Number of Channels, Resolution, Architecture, MSL Level.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC1012D080HN/C1:5
✅ 드롭인✓ 재고 있음
$12.1 / 개
데이터시트 보기 →ADC1010S105HN/C1:5
✅ 드롭인✓ 재고 있음
$9.62 / 개
데이터시트 보기 →ADC1010S080HN/C1:5
✅ 드롭인✓ 재고 있음
$7.32 / 개
데이터시트 보기 →ADS62P22IRGC25
✅ 드롭인✓ 재고 있음
$15.5 / 개
데이터시트 보기 →ADS62P23IRGC25
✅ 드롭인✓ 재고 있음
$18.85 / 개
데이터시트 보기 →ADC1012D125HN/C1:5 최대 정격 & 전기적 특성
| 분해능 | 10 bits |
| Sample Rate (per channel) | 125 MSPS |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined with foreground calibration |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 3.3 V or 1.8 V |
| Output Interface | LVDS (DDR) compatible |
| Input Type | Differential analog inputs |
| 패키지 | HVQFN-64 (9x9 mm, SOT804-3) with exposed pad |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Reel Quantity | 500 (1:5 designator) |
ADC1012D125HN/C1:5 핀 구성
| 핀 1 | INA_P — Channel A positive analog input (differential) |
| 핀 2 | INA_N — Channel A negative analog input (differential) |
| 핀 3 | VCM_A — Channel A common-mode voltage bypass |
| 핀 4 | AVDD — Analog 3.3 V supply |
| 핀 5 | AVDD — Analog 3.3 V supply |
| 핀 6 | AGND — Analog ground |
| 핀 7 | REF_P — Internal reference positive decoupling |
| 핀 8 | REF_N — Internal reference negative decoupling |
| 핀 9 | FS — Full-scale range select (per datasheet) |
| 핀 10 | PD — Power-down control input |
| 핀 11 | CLK_P — Differential clock input positive |
| 핀 12 | CLK_N — Differential clock input negative |
| 핀 13 | INB_P — Channel B positive analog input (differential) |
| 핀 14 | INB_N — Channel B negative analog input (differential) |
| 핀 15 | VCM_B — Channel B common-mode voltage bypass |
| 핀 16 | AVDD — Analog 3.3 V supply |
| 핀 17 | AVDD — Analog 3.3 V supply |
| 핀 18 | AGND — Analog ground |
| 핀 19 | AGND — Analog ground |
| 핀 20 | D0A_P — Channel A LVDS data bit 0 positive |
| 핀 21 | D0A_N — Channel A LVDS data bit 0 negative |
| 핀 22 | D1A_P — Channel A LVDS data bit 1 positive |
| 핀 23 | D1A_N — Channel A LVDS data bit 1 negative |
| 핀 24 | D2A_P — Channel A LVDS data bit 2 positive |
| 핀 25 | D2A_N — Channel A LVDS data bit 2 negative |
| 핀 26 | D3A_P — Channel A LVDS data bit 3 positive |
| 핀 27 | D3A_N — Channel A LVDS data bit 3 negative |
| 핀 28 | D4A_P — Channel A LVDS data bit 4 positive |
| 핀 29 | D4A_N — Channel A LVDS data bit 4 negative |
| 핀 30 | DVDDR — Digital output supply (3.3 V) |
| 핀 31 | DGND — Digital ground |
| 핀 32 | D5A_P — Channel A LVDS data bit 5 positive |
| 핀 33 | D5A_N — Channel A LVDS data bit 5 negative |
| 핀 34 | D6A_P — Channel A LVDS data bit 6 positive |
| 핀 35 | D6A_N — Channel A LVDS data bit 6 negative |
| 핀 36 | D7A_P — Channel A LVDS data bit 7 positive |
| 핀 37 | D7A_N — Channel A LVDS data bit 7 negative |
| 핀 38 | D8A_P — Channel A LVDS data bit 8 positive |
| 핀 39 | D8A_N — Channel A LVDS data bit 8 negative |
| 핀 40 | D9A_P — Channel A LVDS data bit 9 (MSB) positive |
| 핀 41 | D9A_N — Channel A LVDS data bit 9 (MSB) negative |
| 핀 42 | ORA_P — Channel A out-of-range bit positive |
| 핀 43 | ORA_N — Channel A out-of-range bit negative |
| 핀 44 | DRA_P — Channel A data-ready bit positive |
| 핀 45 | DRA_N — Channel A data-ready bit negative |
| 핀 46 | CLKOUT_P — LVDS output clock positive |
| 핀 47 | CLKOUT_N — LVDS output clock negative |
| 핀 48 | D0B_P — Channel B LVDS data bit 0 positive |
| 핀 49 | D0B_N — Channel B LVDS data bit 0 negative |
| 핀 50 | D1B_P — Channel B LVDS data bit 1 positive |
| 핀 51 | D1B_N — Channel B LVDS data bit 1 negative |
| 핀 52 | D2B_P — Channel B LVDS data bit 2 positive |
| 핀 53 | D2B_N — Channel B LVDS data bit 2 negative |
| 핀 54 | D3B_P — Channel B LVDS data bit 3 positive |
| 핀 55 | D3B_N — Channel B LVDS data bit 3 negative |
| 핀 56 | D4B_P — Channel B LVDS data bit 4 positive |
| 핀 57 | D4B_N — Channel B LVDS data bit 4 negative |
| 핀 58 | D5B_P — Channel B LVDS data bit 5 positive |
| 핀 59 | D5B_N — Channel B LVDS data bit 5 negative |
| 핀 60 | D6B_P — Channel B LVDS data bit 6 positive |
| 핀 61 | D6B_N — Channel B LVDS data bit 6 negative |
| 핀 62 | D7B_P — Channel B LVDS data bit 7 positive |
| 핀 63 | D7B_N — Channel B LVDS data bit 7 negative |
| 핀 64 | DGND — Digital ground (multiple pins per datasheet) |
일반적인 애플리케이션
ADC1012D125HN/C1:5 적합 용도: 6 애플리케이션s: Cellular Base-Station Receiver, Software-Defined Radio (SDR) Platform, Medical Ultrasound Beamformer, Radar Signal Processing, High-Speed Instrumentation, Industrial Non-Destructive Testing.
Cellular Base-Station Receiver
The ADC1012D125HN/C1:5's 125 MSPS per channel sample rate and dual simultaneous-sampling channels make it well suited to multi-carrier cellular base-station receivers. Each channel can digitize a separate antenna branch or a separate intermediate-frequency band, enabling diversity reception and MIMO front-end designs in LTE and 5G NR base stations. The pipelined architecture preserves spurious-free dynamic range across the cellular band, while the LVDS DDR output simplifies routing into the FPGA baseband processor.
추천
Software-Defined Radio (SDR) Platform
The ADC1012D125HN/C1:5's high sample rate allows direct-IF or direct-RF sampling in wideband software-defined radio platforms, eliminating one or more analog mixing stages. The dual-channel architecture captures I and Q simultaneously, preserving phase coherence for quadrature demodulation. Its 10-bit resolution offers enough dynamic range for amateur, public-safety, and light-commercial SDR receivers, while the LVDS output simplifies connection to FPGA or DSP processors running the demodulation firmware.
추천
Medical Ultrasound Beamformer
In phased-array medical ultrasound systems, each transducer channel must be sampled simultaneously to preserve beamforming accuracy, and the ADC1012D125HN/C1:5's dual-channel simultaneous-sampling feature supports multi-element probe designs. The 125 MSPS rate comfortably exceeds the Nyquist requirement for typical ultrasound bandwidths (up to ~40 MHz), and the LVDS output cleanly interfaces to the FPGA beamformer. The exposed thermal pad of the HVQFN-64 package allows dense channel arrays on the same PCB.
추천
Radar Signal Processing
The ADC1012D125HN/C1:5 supports radar IF sampling in short-range surveillance, automotive radar, and instrumentation radar front-ends. Its dual-channel architecture captures both in-phase and quadrature returns from a single IF stage, while the pipelined architecture preserves the high SFDR required for distinguishing small targets against clutter. The 125 MSPS rate handles bandwidths typical of FMCW and pulsed-Doppler radar designs.
추천
High-Speed Instrumentation
Bench-top oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers benefit from the ADC1012D125HN/C1:5's 125 MSPS sample rate and dual-channel architecture. The two channels can be interleaved to provide a higher aggregate rate for time-interleaved digitizers, or used independently for two-channel instruments. The LVDS DDR output simplifies routing into the FPGA display processor, while the pipelined architecture delivers the linearity needed for accurate amplitude measurements.
추천
Industrial Non-Destructive Testing
Industrial non-destructive testing (NDT) equipment such as ultrasonic flaw detectors and eddy-current instruments uses high-speed ADCs to capture transient return signals. The ADC1012D125HN/C1:5's dual-channel capability supports phased-array probes or simultaneous transmit/receive paths, while its 125 MSPS rate resolves the bandwidth of typical flaw echoes. The pipelined architecture with foreground calibration maintains measurement accuracy over temperature, which is critical for field-portable NDT equipment.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1012D125HN/C1:5 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1012D080HN/C1:5 | ADC1010S105HN/C1:5 | ADC1010S080HN/C1:5 | ADS62P22IRGC25 | ADS62P23IRGC25 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | Texas Instruments | Texas Instruments |
| Package | HVQFN-64 (9x9 mm, SOT804-3) | HVQFN-64 (9x9 mm) - same | HVQFN-64 (9x9 mm) - same | HVQFN-64 (9x9 mm) - same | QFN-64 RGZ (9x9 mm) - compatible footprint | QFN-64 RGZ (9x9 mm) - compatible footprint |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 12 bits | 12 bits |
| Sample Rate (per channel) | 125 MSPS | 80 MSPS | 105 MSPS | 80 MSPS | 65 MSPS | 80 MSPS |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 1 | 1 | 2 | 2 |
| Output Interface | LVDS DDR | LVDS DDR | LVDS DDR | LVDS DDR | LVDS | LVDS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
주요 차별점
- Highest sample rate in the NXP ADC1010/ADC1012 dual pipelined family (vs ADC1012D080HN/C1:5)
- Dual simultaneous-sampling channels in a single 9x9 mm package (vs ADC1010S105HN/C1:5)
- LVDS DDR digital output at 10-bit resolution (vs ADS62P22IRGC25)
설계 노트
Use a four-layer PCB with dedicated analog and digital ground planes joined only at the exposed thermal pad of the HVQFN-64 package. Place 0.1 µF X7R ceramic decoupling capacitors as close as possible to every AVDD and DVDDR pin, and add 10 µF bulk capacitors near the analog supply entry point. The exposed pad must be soldered to a copper land pattern with at least nine thermal vias (0.3 mm drill) to keep junction temperature within the datasheet limits at full 125 MSPS dual-channel operation.
Route LVDS data pairs as 100 Ω differential transmission lines with matched length (±150 mil) within each channel and across channels to maintain DDR timing alignment at the FPGA. Keep LVDS traces away from analog input traces and from switching power supply nodes; place a continuous ground reference beneath the LVDS routes. Source-terminate the clock pair at the FPGA end with 100 Ω to minimize reflections.
Do not operate the ADC1012D125HN/C1:5 without a valid differential clock on CLK± - the LVDS outputs will not be defined. Ensure the clock duty cycle is within 45/55 percent and that the clock common-mode voltage is within the datasheet range. Avoid routing the analog inputs across noisy digital planes, as the LVDS DDR switching at 250 MHz can couple into the analog sampling network and degrade SFDR by several dB.
Power sequencing: bring up AVDD first, then DVDDR, then apply the clock and analog inputs. If sequencing is not possible, the PD (power-down) pin can be held low during supply ramp to keep the analog front-end in a known state. Estimate: at 125 MSPS dual-channel operation, total dissipation is approximately 700 mW, so the 3.3 V analog regulator must supply at least 250 mA with adequate headroom for transient load steps during sample edges.
규정 준수 정보
RoHS and REACH compliance inferred from NXP product page lead-free HVQFN packaging; AEC-Q100 not applicable for commercial-grade ADC. Halogen-free status not explicitly stated in the verified data - left as unknown.
