ADS808Y/250G4 - 12-Bit 70MSPS Pipelined ADC | Texas Instruments
부품 번호: ADS808Y/250G4 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.95 | $129.50 |
| 100 | $11.2 | $1,120.00 |
| 500 | $9.85 | $4,925.00 |
| 1,000 | $8.95 | $8,950.00 |
ADS808Y/250G4 개요
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a sampling rate set by an external clock. Pipelined ADCs like the ADS808 use multiple low-resolution flash stages cascaded behind a high-bandwidth SHA, trading modest latency for very high sampling rates at moderate resolution. They sit within the broader hierarchy: ADC -> data converter -> mixed-signal IC -> power-management-and-signal-chain semiconductor.
Key features include 70 MSPS guaranteed sampling rate, 12-bit resolution with no missing codes, selectable 1.0 Vpp or 2.0 Vpp full-scale input range, internal or external reference, and a low-jitter differential or single-ended clock input that accepts sine or square signals down to 0.5 Vp-p. The 48-HTQFP powerPAD package provides a thermal resistance of approximately 25 C/W with sufficient copper area, enabling reliable operation up to the 70 MHz clock rate.
The architecture is a 12-stage pipelined ADC with digital error correction. Its track-and-hold bandwidth exceeds 100 MHz, and aperture jitter is specified at 0.25 ps rms, which is critical for preserving SNR when digitising IF signals above 30 MHz. Output data is delivered via a parallel CMOS interface compatible with standard DSPs and FPGAs.
Typical applications include medical ultrasound imaging, digital video broadcast demodulation, CCD imaging digitisation, IF sampling in communications receivers, and industrial test instrumentation. The wide input bandwidth makes it particularly attractive for undersampling IF stages.
When designing with this device, allocate adequate ground and supply decoupling (100 nF ceramic close to each supply pin plus a 10 uF bulk), and provide at least 1 square inch of PCB copper beneath the exposed pad. The /PD pin should be tied high for normal operation and pulled low for powerdown, reducing quiescent current for portable or energy-aware platforms.
This page synthesizes distributor pricing, drop-in package-compatible alternatives, and practical PCB design guidance not always presented together in the manufacturer datasheet, giving engineers a single source for sourcing, selection, and layout decisions.
드롭인 대체품: ADS808Y/250G4 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADS808Y/250G4 (동일 폼 팩터 및 풋프린트) — 차이점: Analog Supply Voltage, Digital Supply Voltage, Full-Scale Input Range, Input Type, Package.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADS808Y/250
✅ 드롭인✓ 재고 있음
$8.4 / 개
데이터시트 보기 →ADS808Y/1KG4
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS809Y/250
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS810Y/250
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ADS808Y/250G4 최대 정격 & 전기적 특성
| 분해능 | 12 bit |
| 샘플링 속도 | 70 MSPS |
| Number of Inputs | 1 (single channel) |
| Architecture | Pipelined |
| Input Type | Differential / Single-Ended (selectable) |
| Data Interface | Parallel CMOS |
| Analog Supply Voltage | 4.75 V to 5.25 V (5 V nominal) |
| Digital Supply Voltage | 3 V to 5 V |
| Full-Scale Input Range | 1.0 Vpp or 2.0 Vpp (selectable) |
| Reference | Internal or External (selectable) |
| Aperture Jitter | 0.25 ps rms |
| SNR | 68 dB typical at fIN = 10 MHz |
| SFDR | 74 dB typical at fIN = 10 MHz |
| 동작 온도 | -40 C to +85 C |
| 패키지 | 48-HTQFP (PHP) PowerPAD, 7x7 mm |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
ADS808Y/250G4 핀 구성
| 핀 1 | AVDD |
| 핀 2 | IN+ — Differential analog input positive |
| 핀 3 | IN- — Differential analog input negative |
| 핀 4 | AGND — Analog ground |
| 핀 5 | REFT — Internal reference top (decoupling) |
| 핀 6 | REFB — Internal reference bottom (decoupling) |
| 핀 7 | REFOUT — Internal reference output |
| 핀 8 | REFIN — External reference input |
| 핀 9 | FS — Full-scale select (1.0 Vpp / 2.0 Vpp) |
| 핀 10 | PD — Powerdown (active low) |
| 핀 11 | CLOCK+ — Differential clock input positive |
| 핀 12 | CLOCK- — Differential clock input negative |
| 핀 13 | AGND — Analog ground |
| 핀 14 | AVDD |
| 핀 15 | NC — Not connected (per datasheet) |
| 핀 16 | NC — Not connected (per datasheet) |
| 핀 17 | DVDD |
| 핀 18 | DGND — Digital ground |
| 핀 19 | D11 — Data output bit 11 (MSB) |
| 핀 20 | D10 — Data output bit 10 |
| 핀 21 | D9 — Data output bit 9 |
| 핀 22 | D8 — Data output bit 8 |
| 핀 23 | D7 — Data output bit 7 |
| 핀 24 | D6 — Data output bit 6 |
| 핀 25 | D5 — Data output bit 5 |
| 핀 26 | D4 — Data output bit 4 |
| 핀 27 | D3 — Data output bit 3 |
| 핀 28 | D2 — Data output bit 2 |
| 핀 29 | D1 — Data output bit 1 |
| 핀 30 | D0 — Data output bit 0 (LSB) |
| 핀 31 | NC — Not connected (per datasheet) |
| 핀 32 | NC — Not connected (per datasheet) |
| 핀 33 | NC — Not connected (per datasheet) |
| 핀 34 | NC — Not connected (per datasheet) |
| 핀 35 | NC — Not connected (per datasheet) |
| 핀 36 | NC — Not connected (per datasheet) |
| 핀 37 | NC — Not connected (per datasheet) |
| 핀 38 | NC — Not connected (per datasheet) |
| 핀 39 | NC — Not connected (per datasheet) |
| 핀 40 | NC — Not connected (per datasheet) |
| 핀 41 | NC — Not connected (per datasheet) |
| 핀 42 | NC — Not connected (per datasheet) |
| 핀 43 | NC — Not connected (per datasheet) |
| 핀 44 | NC — Not connected (per datasheet) |
| 핀 45 | NC — Not connected (per datasheet) |
| 핀 46 | NC — Not connected (per datasheet) |
| 핀 47 | NC — Not connected (per datasheet) |
| 핀 48 | PowerPAD — Exposed thermal pad - solder to ground plane |
일반적인 애플리케이션
ADS808Y/250G4 적합 용도: 6 애플리케이션s: Medical Ultrasound Imaging, IF Sampling in Communications Receivers, Digital Video Broadcast Demodulation, CCD Imaging Digitisation, Industrial Test Instrumentation, Portable / Battery-Powered Data Acquisition.
Medical Ultrasound Imaging
The ADS808Y/250G4's 70 MSPS sample rate and 0.25 ps rms aperture jitter make it well suited to medical ultrasound front-end digitisation, where echo bandwidth from deep tissue can extend to 20-30 MHz. The 12-bit resolution provides approximately 68 dB SNR at 10 MHz input, sufficient to resolve subtle tissue contrast differences after beamforming. The pipelined architecture introduces only 5 clock cycles of latency, acceptable for real-time B-mode imaging where deterministic delay matters less than throughput. The 48-HTQFP PowerPAD package dissipates roughly 400 mW at full sample rate; a 1 square inch copper pour keeps junction temperature rise below 25 C. Compared with older 8-bit ultrasound ADCs, this 12-bit pipelined part extends dynamic range by roughly 6 dB per bit and enables harmonic imaging modes that demand lower noise floor for second-harmonic echo detection.
추천
IF Sampling in Communications Receivers
The ADS808Y/250G4 supports undersampling of IF stages in digital communications receivers, where signals centred at 21.4 MHz, 36.4 MHz, or 44 MHz can be directly digitised at 70 MSPS without a preceding downconversion mixer. The 0.25 ps rms aperture jitter preserves SNR up to roughly 70 MHz input - critical because aperture jitter dominates noise budget above 30 MHz IF. Selectable 1.0 Vpp or 2.0 Vpp full-scale range lets designers optimise SNR versus headroom for the specific IF signal amplitude. Differential clock input down to 0.5 Vp-p allows direct drive from a TCXO without a clock buffer, reducing board complexity. The pipelined architecture's five-cycle latency is acceptable for block-oriented demodulation where the receiver can buffer digital samples through an FPGA.
추천
Digital Video Broadcast Demodulation
DVB-T and ATSC demodulators require precise digitisation of IF outputs from the tuner at sample rates matching the symbol clock after digital resampling. The ADS808Y/250G4's 70 MSPS throughput provides 2x or 4x oversampling of typical 36 MHz or 44 MHz IF signals, easing the analog anti-alias filter requirement. The 12-bit dynamic range is well matched to the MER requirements of 8-VSB and OFDM carriers. The selectable full-scale input range of 1.0 Vpp or 2.0 Vpp allows direct interface with most tuner AGC ranges without external attenuators. The CMOS parallel output integrates cleanly with demodulator ASICs and FPGAs without requiring an external serializer. Powerdown mode enables standby operation during channel-survey scans.
추천
CCD Imaging Digitisation
The ADS808Y/250G4 is well suited for CCD line-scan and area-scan camera digitisation, where pixel clock rates up to 70 MHz demand high throughput and low noise. The 12-bit resolution captures the full dynamic range of typical scientific and machine-vision CCDs, and the 0.25 ps jitter preserves SNR even for short exposure pixels. The selectable full-scale range of 1.0 Vpp or 2.0 Vpp accommodates the variable output amplitudes of different CCD manufacturers. Differential clock input rejects common-mode noise from the pixel clock distribution network. Powerdown mode supports inter-frame blanking, reducing average system power when continuous streaming is not required. The 48-HTQFP package fits within standard camera head board form factors.
추천
Industrial Test Instrumentation
The ADS808Y/250G4's combination of 12-bit resolution, 70 MSPS sample rate, and excellent SNR makes it a strong choice for digitising wideband signals in oscilloscopes, spectrum analysers, and arbitrary waveform digitiser instruments. The pipelined architecture's deterministic latency simplifies trigger placement and time-base calibration. Selectable full-scale input range allows the same board design to handle both small and large amplitude signals with appropriate attenuation. The exposed-pad PowerPAD package provides stable thermal performance for continuous full-rate acquisition. Internal reference option eliminates external reference drift in field-portable instruments. The CMOS parallel interface feeds directly into FPGAs for inline DSP and waveform reconstruction.
추천
Portable / Battery-Powered Data Acquisition
The ADS808Y/250G4's powerdown pin enables duty-cycled operation in battery-powered data acquisition systems such as handheld ultrasound probes, portable spectrum analysers, and field instrumentation. When idle, the device drops to microamp-level quiescent current, and wakeup time is fast enough for burst-mode sampling. The 5 V analog supply is compatible with common USB and Li-ion boost regulator rails. The compact 48-HTQFP package allows dense PCB layouts, while the exposed pad provides sufficient thermal dissipation for intermittent full-rate sampling. The flexible reference (internal or external) lets designers trade absolute accuracy for BOM cost depending on calibration strategy. Differential clock input rejects noise from switching regulators common in portable designs.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADS808Y/250G4 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADS808Y/250 | ADS808Y/1KG4 | ADS809Y/250 | ADS810Y/250 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-HTQFP (PHP) PowerPAD 7x7 mm | 48-HTQFP (PHP) PowerPAD 7x7 mm - same | 48-HTQFP (PHP) PowerPAD 7x7 mm - same | 48-HTQFP (PHP) PowerPAD 7x7 mm - same | 48-HTQFP (PHP) PowerPAD 7x7 mm - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 70 MSPS | 70 MSPS | 70 MSPS | 80 MSPS | 80 MSPS |
| Aperture Jitter | 0.25 ps rms | 0.25 ps rms | 0.25 ps rms | 0.25 ps rms | 0.25 ps rms |
| Analog Supply | 5 V | 5 V | 5 V | 5 V | 5 V |
| Reel Quantity | 250 | 250 (non-G4 reel code) | 1000 | 250 | 250 |
주요 차별점
- True 70 MSPS pipelined ADC in compact 48-HTQFP PowerPAD (vs ADS808Y/250 (base /250 reel code))
- Higher sample rate available in same footprint (vs ADS809Y/250 and ADS810Y/250)
- Selectable 1.0 Vpp or 2.0 Vpp full-scale input (vs ADS7805PG4 (12-bit 100 kSPS, 28-SOIC))
- Premium 0.25 ps rms aperture jitter for high-IF sampling (vs ADS7806PG4 (12-bit 40 kSPS, 28-SOIC))
설계 노트
The ADS808Y/250G4's exposed PowerPAD must be soldered directly to a ground-plane copper pour of at least 1 square inch (645 mm^2) on the top or inner PCB layer. Use an array of 0.3 mm thermal vias on 1.0 mm pitch connecting the pad to internal ground planes to achieve the datasheet-specified thermal resistance of approximately 25 C/W. Insufficient thermal relief can cause junction temperature to exceed 125 C under continuous 70 MSPS operation.
Place a 100 nF X7R ceramic decoupling capacitor within 3 mm of every AVDD pin and a 10 uF tantalum or ceramic bulk capacitor on each supply rail. Keep analog and digital ground returns separated back to a single point beneath the device, and use a pi-filter (ferrite bead plus capacitor) on the analog 5 V supply rail to block digital switching noise from corrupting the analog front-end.
Do not leave the FS (full-scale select) pin floating; it must be tied high or low for a defined full-scale range. Floating CLOCK+ and CLOCK- inputs can pick up noise and cause spurious codes; if driven single-ended, terminate the unused input with 50 ohm to the mid-supply bias. The /PD pin must be tied high through a 10 kohm resistor for normal operation - never leave it floating.
Route the analog input traces as a 50 ohm controlled-impedance differential pair with matched lengths to within 0.5 mm, and keep them away from digital output buses. The clock input should be treated as a high-frequency analog signal: short traces, ground shielding, and series termination close to the driver. Maintain solid ground plane under the analog input traces to avoid slot-line effects.
Estimated: at 5 V analog supply, 70 MSPS continuous operation, and worst-case load (full-scale sine input), the ADS808Y/250G4 dissipates approximately 400 mW. With a 25 C/W theta_JA (achieved with 1 sq inch of copper), junction temperature rises about 10 C above ambient. At 85 C ambient, the junction reaches 95 C, leaving roughly 30 C margin to the 125 C maximum.
규정 준수 정보
The G4 suffix denotes Pb-free green finish per TI product page. AEC-Q100 not qualified - this part targets industrial, medical, and communications applications rather than automotive. Halogen-free per TI Material Composition Declaration.
