ADS808Y/250G4 - 12-Bit 70MSPS Pipelined ADC | Texas Instruments
N.º da peça: ADS808Y/250G4 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $14.5 | $14,50 |
| 10 | $12.95 | $129,50 |
| 100 | $11.2 | $1.120,00 |
| 500 | $9.85 | $4.925,00 |
| 1.000 | $8.95 | $8.950,00 |
ADS808Y/250G4 Visão geral
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a sampling rate set by an external clock. Pipelined ADCs like the ADS808 use multiple low-resolution flash stages cascaded behind a high-bandwidth SHA, trading modest latency for very high sampling rates at moderate resolution. They sit within the broader hierarchy: ADC -> data converter -> mixed-signal IC -> power-management-and-signal-chain semiconductor.
Key features include 70 MSPS guaranteed sampling rate, 12-bit resolution with no missing codes, selectable 1.0 Vpp or 2.0 Vpp full-scale input range, internal or external reference, and a low-jitter differential or single-ended clock input that accepts sine or square signals down to 0.5 Vp-p. The 48-HTQFP powerPAD package provides a thermal resistance of approximately 25 C/W with sufficient copper area, enabling reliable operation up to the 70 MHz clock rate.
The architecture is a 12-stage pipelined ADC with digital error correction. Its track-and-hold bandwidth exceeds 100 MHz, and aperture jitter is specified at 0.25 ps rms, which is critical for preserving SNR when digitising IF signals above 30 MHz. Output data is delivered via a parallel CMOS interface compatible with standard DSPs and FPGAs.
Typical applications include medical ultrasound imaging, digital video broadcast demodulation, CCD imaging digitisation, IF sampling in communications receivers, and industrial test instrumentation. The wide input bandwidth makes it particularly attractive for undersampling IF stages.
When designing with this device, allocate adequate ground and supply decoupling (100 nF ceramic close to each supply pin plus a 10 uF bulk), and provide at least 1 square inch of PCB copper beneath the exposed pad. The /PD pin should be tied high for normal operation and pulled low for powerdown, reducing quiescent current for portable or energy-aware platforms.
This page synthesizes distributor pricing, drop-in package-compatible alternatives, and practical PCB design guidance not always presented together in the manufacturer datasheet, giving engineers a single source for sourcing, selection, and layout decisions.
Alternativas drop-in para ADS808Y/250G4 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADS808Y/250G4 (mesmo formato e footprint) — diferindo em Analog Supply Voltage, Digital Supply Voltage, Full-Scale Input Range, Input Type, Package.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADS808Y/250
✅ Drop-In✓ Em estoque
$8.4 / unidade
Ver ficha técnica →ADS808Y/1KG4
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS809Y/250
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS810Y/250
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADS808Y/250G4 Classificações máximas e características elétricas
| Resolução | 12 bit |
| Taxa de amostragem | 70 MSPS |
| Number of Inputs | 1 (single channel) |
| Architecture | Pipelined |
| Input Type | Differential / Single-Ended (selectable) |
| Data Interface | Parallel CMOS |
| Analog Supply Voltage | 4.75 V to 5.25 V (5 V nominal) |
| Digital Supply Voltage | 3 V to 5 V |
| Full-Scale Input Range | 1.0 Vpp or 2.0 Vpp (selectable) |
| Reference | Internal or External (selectable) |
| Aperture Jitter | 0.25 ps rms |
| SNR | 68 dB typical at fIN = 10 MHz |
| SFDR | 74 dB typical at fIN = 10 MHz |
| Temperatura de operação | -40 C to +85 C |
| Encapsulamento | 48-HTQFP (PHP) PowerPAD, 7x7 mm |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Lead-Free | Yes |
Configuração de pinos do ADS808Y/250G4
| Pino 1 | AVDD |
| Pino 2 | IN+ — Differential analog input positive |
| Pino 3 | IN- — Differential analog input negative |
| Pino 4 | AGND — Analog ground |
| Pino 5 | REFT — Internal reference top (decoupling) |
| Pino 6 | REFB — Internal reference bottom (decoupling) |
| Pino 7 | REFOUT — Internal reference output |
| Pino 8 | REFIN — External reference input |
| Pino 9 | FS — Full-scale select (1.0 Vpp / 2.0 Vpp) |
| Pino 10 | PD — Powerdown (active low) |
| Pino 11 | CLOCK+ — Differential clock input positive |
| Pino 12 | CLOCK- — Differential clock input negative |
| Pino 13 | AGND — Analog ground |
| Pino 14 | AVDD |
| Pino 15 | NC — Not connected (per datasheet) |
| Pino 16 | NC — Not connected (per datasheet) |
| Pino 17 | DVDD |
| Pino 18 | DGND — Digital ground |
| Pino 19 | D11 — Data output bit 11 (MSB) |
| Pino 20 | D10 — Data output bit 10 |
| Pino 21 | D9 — Data output bit 9 |
| Pino 22 | D8 — Data output bit 8 |
| Pino 23 | D7 — Data output bit 7 |
| Pino 24 | D6 — Data output bit 6 |
| Pino 25 | D5 — Data output bit 5 |
| Pino 26 | D4 — Data output bit 4 |
| Pino 27 | D3 — Data output bit 3 |
| Pino 28 | D2 — Data output bit 2 |
| Pino 29 | D1 — Data output bit 1 |
| Pino 30 | D0 — Data output bit 0 (LSB) |
| Pino 31 | NC — Not connected (per datasheet) |
| Pino 32 | NC — Not connected (per datasheet) |
| Pino 33 | NC — Not connected (per datasheet) |
| Pino 34 | NC — Not connected (per datasheet) |
| Pino 35 | NC — Not connected (per datasheet) |
| Pino 36 | NC — Not connected (per datasheet) |
| Pino 37 | NC — Not connected (per datasheet) |
| Pino 38 | NC — Not connected (per datasheet) |
| Pino 39 | NC — Not connected (per datasheet) |
| Pino 40 | NC — Not connected (per datasheet) |
| Pino 41 | NC — Not connected (per datasheet) |
| Pino 42 | NC — Not connected (per datasheet) |
| Pino 43 | NC — Not connected (per datasheet) |
| Pino 44 | NC — Not connected (per datasheet) |
| Pino 45 | NC — Not connected (per datasheet) |
| Pino 46 | NC — Not connected (per datasheet) |
| Pino 47 | NC — Not connected (per datasheet) |
| Pino 48 | PowerPAD — Exposed thermal pad - solder to ground plane |
Aplicações típicas
ADS808Y/250G4 é adequado para 6 aplicaçãos: Medical Ultrasound Imaging, IF Sampling in Communications Receivers, Digital Video Broadcast Demodulation, CCD Imaging Digitisation, Industrial Test Instrumentation, Portable / Battery-Powered Data Acquisition.
Medical Ultrasound Imaging
The ADS808Y/250G4's 70 MSPS sample rate and 0.25 ps rms aperture jitter make it well suited to medical ultrasound front-end digitisation, where echo bandwidth from deep tissue can extend to 20-30 MHz. The 12-bit resolution provides approximately 68 dB SNR at 10 MHz input, sufficient to resolve subtle tissue contrast differences after beamforming. The pipelined architecture introduces only 5 clock cycles of latency, acceptable for real-time B-mode imaging where deterministic delay matters less than throughput. The 48-HTQFP PowerPAD package dissipates roughly 400 mW at full sample rate; a 1 square inch copper pour keeps junction temperature rise below 25 C. Compared with older 8-bit ultrasound ADCs, this 12-bit pipelined part extends dynamic range by roughly 6 dB per bit and enables harmonic imaging modes that demand lower noise floor for second-harmonic echo detection.
Recomendado
IF Sampling in Communications Receivers
The ADS808Y/250G4 supports undersampling of IF stages in digital communications receivers, where signals centred at 21.4 MHz, 36.4 MHz, or 44 MHz can be directly digitised at 70 MSPS without a preceding downconversion mixer. The 0.25 ps rms aperture jitter preserves SNR up to roughly 70 MHz input - critical because aperture jitter dominates noise budget above 30 MHz IF. Selectable 1.0 Vpp or 2.0 Vpp full-scale range lets designers optimise SNR versus headroom for the specific IF signal amplitude. Differential clock input down to 0.5 Vp-p allows direct drive from a TCXO without a clock buffer, reducing board complexity. The pipelined architecture's five-cycle latency is acceptable for block-oriented demodulation where the receiver can buffer digital samples through an FPGA.
Recomendado
Digital Video Broadcast Demodulation
DVB-T and ATSC demodulators require precise digitisation of IF outputs from the tuner at sample rates matching the symbol clock after digital resampling. The ADS808Y/250G4's 70 MSPS throughput provides 2x or 4x oversampling of typical 36 MHz or 44 MHz IF signals, easing the analog anti-alias filter requirement. The 12-bit dynamic range is well matched to the MER requirements of 8-VSB and OFDM carriers. The selectable full-scale input range of 1.0 Vpp or 2.0 Vpp allows direct interface with most tuner AGC ranges without external attenuators. The CMOS parallel output integrates cleanly with demodulator ASICs and FPGAs without requiring an external serializer. Powerdown mode enables standby operation during channel-survey scans.
Recomendado
CCD Imaging Digitisation
The ADS808Y/250G4 is well suited for CCD line-scan and area-scan camera digitisation, where pixel clock rates up to 70 MHz demand high throughput and low noise. The 12-bit resolution captures the full dynamic range of typical scientific and machine-vision CCDs, and the 0.25 ps jitter preserves SNR even for short exposure pixels. The selectable full-scale range of 1.0 Vpp or 2.0 Vpp accommodates the variable output amplitudes of different CCD manufacturers. Differential clock input rejects common-mode noise from the pixel clock distribution network. Powerdown mode supports inter-frame blanking, reducing average system power when continuous streaming is not required. The 48-HTQFP package fits within standard camera head board form factors.
Recomendado
Industrial Test Instrumentation
The ADS808Y/250G4's combination of 12-bit resolution, 70 MSPS sample rate, and excellent SNR makes it a strong choice for digitising wideband signals in oscilloscopes, spectrum analysers, and arbitrary waveform digitiser instruments. The pipelined architecture's deterministic latency simplifies trigger placement and time-base calibration. Selectable full-scale input range allows the same board design to handle both small and large amplitude signals with appropriate attenuation. The exposed-pad PowerPAD package provides stable thermal performance for continuous full-rate acquisition. Internal reference option eliminates external reference drift in field-portable instruments. The CMOS parallel interface feeds directly into FPGAs for inline DSP and waveform reconstruction.
Recomendado
Portable / Battery-Powered Data Acquisition
The ADS808Y/250G4's powerdown pin enables duty-cycled operation in battery-powered data acquisition systems such as handheld ultrasound probes, portable spectrum analysers, and field instrumentation. When idle, the device drops to microamp-level quiescent current, and wakeup time is fast enough for burst-mode sampling. The 5 V analog supply is compatible with common USB and Li-ion boost regulator rails. The compact 48-HTQFP package allows dense PCB layouts, while the exposed pad provides sufficient thermal dissipation for intermittent full-rate sampling. The flexible reference (internal or external) lets designers trade absolute accuracy for BOM cost depending on calibration strategy. Differential clock input rejects noise from switching regulators common in portable designs.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADS808Y/250G4 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADS808Y/250 | ADS808Y/1KG4 | ADS809Y/250 | ADS810Y/250 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-HTQFP (PHP) PowerPAD 7x7 mm | 48-HTQFP (PHP) PowerPAD 7x7 mm - same | 48-HTQFP (PHP) PowerPAD 7x7 mm - same | 48-HTQFP (PHP) PowerPAD 7x7 mm - same | 48-HTQFP (PHP) PowerPAD 7x7 mm - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 70 MSPS | 70 MSPS | 70 MSPS | 80 MSPS | 80 MSPS |
| Aperture Jitter | 0.25 ps rms | 0.25 ps rms | 0.25 ps rms | 0.25 ps rms | 0.25 ps rms |
| Analog Supply | 5 V | 5 V | 5 V | 5 V | 5 V |
| Reel Quantity | 250 | 250 (non-G4 reel code) | 1000 | 250 | 250 |
Principais diferenciais
- True 70 MSPS pipelined ADC in compact 48-HTQFP PowerPAD (vs ADS808Y/250 (base /250 reel code))
- Higher sample rate available in same footprint (vs ADS809Y/250 and ADS810Y/250)
- Selectable 1.0 Vpp or 2.0 Vpp full-scale input (vs ADS7805PG4 (12-bit 100 kSPS, 28-SOIC))
- Premium 0.25 ps rms aperture jitter for high-IF sampling (vs ADS7806PG4 (12-bit 40 kSPS, 28-SOIC))
Notas de projeto
The ADS808Y/250G4's exposed PowerPAD must be soldered directly to a ground-plane copper pour of at least 1 square inch (645 mm^2) on the top or inner PCB layer. Use an array of 0.3 mm thermal vias on 1.0 mm pitch connecting the pad to internal ground planes to achieve the datasheet-specified thermal resistance of approximately 25 C/W. Insufficient thermal relief can cause junction temperature to exceed 125 C under continuous 70 MSPS operation.
Place a 100 nF X7R ceramic decoupling capacitor within 3 mm of every AVDD pin and a 10 uF tantalum or ceramic bulk capacitor on each supply rail. Keep analog and digital ground returns separated back to a single point beneath the device, and use a pi-filter (ferrite bead plus capacitor) on the analog 5 V supply rail to block digital switching noise from corrupting the analog front-end.
Do not leave the FS (full-scale select) pin floating; it must be tied high or low for a defined full-scale range. Floating CLOCK+ and CLOCK- inputs can pick up noise and cause spurious codes; if driven single-ended, terminate the unused input with 50 ohm to the mid-supply bias. The /PD pin must be tied high through a 10 kohm resistor for normal operation - never leave it floating.
Route the analog input traces as a 50 ohm controlled-impedance differential pair with matched lengths to within 0.5 mm, and keep them away from digital output buses. The clock input should be treated as a high-frequency analog signal: short traces, ground shielding, and series termination close to the driver. Maintain solid ground plane under the analog input traces to avoid slot-line effects.
Estimated: at 5 V analog supply, 70 MSPS continuous operation, and worst-case load (full-scale sine input), the ADS808Y/250G4 dissipates approximately 400 mW. With a 25 C/W theta_JA (achieved with 1 sq inch of copper), junction temperature rises about 10 C above ambient. At 85 C ambient, the junction reaches 95 C, leaving roughly 30 C margin to the 125 C maximum.
Informações de conformidade
The G4 suffix denotes Pb-free green finish per TI product page. AEC-Q100 not qualified - this part targets industrial, medical, and communications applications rather than automotive. Halogen-free per TI Material Composition Declaration.
