ATMEGA8535L-8JJ - 8KB AVR MCU, 8MHz, 44-PLCC | Microchip
부품 번호: ATMEGA8535L-8JJ ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $3.54 | $3.54 |
| 10 | $3.35 | $33.50 |
| 100 | $3.1 | $310.00 |
| 500 | $2.9 | $1,450.00 |
| 1,000 | $2.75 | $2,750.00 |
ATMEGA8535L-8JJ 개요
An AVR microcontroller is a family of 8-bit Harvard-architecture MCUs from Microchip (originally Atmel) that executes most instructions in a single clock cycle. Within the product hierarchy, the ATmega8535 sits at: microcontroller -> 8-bit MCU -> AVR ATmega family. Because program memory and data memory are separate buses, the AVR can achieve up to 16 MIPS throughput at 16 MHz, delivering performance typically requiring larger clock speeds in CISC architectures.
Key features include 130 powerful RISC instructions (most single-cycle), 32 general-purpose working registers, 32 programmable I/O lines, and three flexible Timer/Counters with compare modes. The device also integrates a byte-oriented Two-wire Serial Interface (TWI, I2C-compatible), a serial programmable USART, an SPI interface, and internal/external interrupt sources. The 10-bit ADC resolves 8 single-ended channels, suitable for sensor interfaces in cost-sensitive designs.
The L suffix denotes the low-voltage product grade, operating from 2.7V to 5.5V with a maximum clock of 8 MHz, versus the 16 MHz standard grade. Self-programming Flash with Read-While-Write support enables field firmware updates without external programmers, while ISP via SPI simplifies production programming.
Typical applications include industrial control boards, sensor data acquisition systems, motor control auxiliaries, and legacy embedded systems where the 44-PLCC footprint must be maintained for socketed or board-level compatibility.
Designers should note the 8 MHz limit of the L-grade part: designs requiring 16 MHz throughput must use the standard-grade ATmega8535 variant instead.
This page synthesizes verified distributor pricing, drop-in alternatives, pinout details, and practical design notes beyond what the manufacturer datasheet provides.
드롭인 대체품: ATMEGA8535L-8JJ — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ATMEGA8535L-8JJ (동일 폼 팩터 및 풋프린트) — 차이점: Mounting Type, Package, Flash Program Memory, SRAM, ADC.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ATMEGA8535L-8JI
✅ 드롭인✓ 재고 있음
$3.68 / 개
데이터시트 보기 →ATMEGA8535-16PJ
✅ 드롭인✓ 재고 있음
$3.4 / 개
데이터시트 보기 →ATMEGA8535-16JI
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
AT90S8535-8JC
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
ATMEGA8535L-8JJ 최대 정격 & 전기적 특성
| Core Architecture | AVR 8-bit RISC |
| Flash Program Memory | 8 KB |
| SRAM | 512 bytes |
| EEPROM | 512 bytes |
| 최대 클록 주파수 | 8 MHz |
| Maximum Throughput | Up to 16 MIPS at 16 MHz (family) |
| Instructions | 130 powerful instructions, most single-cycle |
| ADC | 8-channel, 10-bit |
| General Purpose I/O | 32 lines |
| Working Registers | 32 general purpose |
| Timers/Counters | Three flexible Timer/Counters with compare modes |
| Serial Interfaces | USART, Two-wire Serial Interface (TWI/I2C-compatible), SPI |
| 패키지 | 44-PLCC (J) |
| 실장 유형 | Surface Mount |
| 핀 수 | 44 |
| Flash Organization | 4K x 16 (self-programming, Read-While-Write) |
| In-System Programming | Yes (ISP via SPI) |
ATMEGA8535L-8JJ 핀 구성
| 핀 1 | PA3 (ADC3) — Port A bit 3 / ADC channel 3 input |
| 핀 2 | PA4 (ADC4) — Port A bit 4 / ADC channel 4 input |
| 핀 3 | PA5 (ADC5) — Port A bit 5 / ADC channel 5 input |
| 핀 4 | PA6 (ADC6) — Port A bit 6 / ADC channel 6 input |
| 핀 5 | PA7 (ADC7) — Port A bit 7 / ADC channel 7 input |
| 핀 6 | AREF — Analog reference voltage for ADC |
| 핀 7 | AVCC — Analog supply voltage for ADC |
| 핀 8 | PB0 (SS) — Port B bit 0 / SPI Slave Select |
| 핀 9 | PB1 (T1) — Port B bit 1 / Timer1 external clock input |
| 핀 10 | PB2 (AIN0) — Port B bit 2 / Analog Comparator positive input |
| 핀 11 | PB3 (AIN1) — Port B bit 3 / Analog Comparator negative input |
| 핀 12 | PB4 (SS) — Port B bit 4 / SPI Slave Select |
| 핀 13 | PB5 (MOSI) — Port B bit 5 / SPI Master Output Slave Input |
| 핀 14 | PB6 (MISO) — Port B bit 6 / SPI Master Input Slave Output |
| 핀 15 | PB7 (SCK/OC0) — Port B bit 7 / SPI Clock or Timer0 output compare |
| 핀 16 | PC0 (SCL) — Port C bit 0 / TWI clock |
| 핀 17 | PC1 (SDA) — Port C bit 1 / TWI data |
| 핀 18 | PC2 (TCK) — Port C bit 2 / JTAG test clock |
| 핀 19 | PC3 (TMS) — Port C bit 3 / JTAG test mode select |
| 핀 20 | PC4 (TDO) — Port C bit 4 / JTAG test data out |
| 핀 21 | PC5 (TDI) — Port C bit 5 / JTAG test data in |
| 핀 22 | PC6 (TOSC1) — Port C bit 6 / Timer oscillator input |
| 핀 23 | PC7 (TOSC2) — Port C bit 7 / Timer oscillator output |
| 핀 24 | PD0 (RXD) — Port D bit 0 / USART receive |
| 핀 25 | PD1 (TXD) — Port D bit 1 / USART transmit |
| 핀 26 | PD2 (INT0) — Port D bit 2 / External interrupt 0 |
| 핀 27 | PD3 (INT1) — Port D bit 3 / External interrupt 1 |
| 핀 28 | PD4 (OC1B) — Port D bit 4 / Timer1 output compare B |
| 핀 29 | PD5 (OC1A) — Port D bit 5 / Timer1 output compare A |
| 핀 30 | PD6 (ICP1) — Port D bit 6 / Timer1 input capture |
| 핀 31 | PD7 (OC2) — Port D bit 7 / Timer2 output compare |
| 핀 32 | VCC — Digital supply voltage |
| 핀 33 | GND — Digital ground |
| 핀 34 | PA0 (ADC0) — Port A bit 0 / ADC channel 0 input |
| 핀 35 | PA1 (ADC1) — Port A bit 1 / ADC channel 1 input |
| 핀 36 | PA2 (ADC2) — Port A bit 2 / ADC channel 2 input |
| 핀 37 | PE0 (ICP3/CLKO) — Alternate-function pin (per datasheet pin configuration) |
| 핀 38 | XTAL1 — External clock input / crystal in |
| 핀 39 | XTAL2 — Crystal output / oscillator amplifier output |
| 핀 40 | RESET — Active-low reset input |
| 핀 41 | NC — Not connected (per datasheet) |
| 핀 42 | NC — Not connected (per datasheet) |
| 핀 43 | NC — Not connected (per datasheet) |
| 핀 44 | NC — Not connected (per datasheet) |
일반적인 애플리케이션
ATMEGA8535L-8JJ 적합 용도: 6 애플리케이션s: Industrial Control Boards, Sensor Data Acquisition Systems, Legacy Embedded System Maintenance, Motor Control Auxiliaries, Instrumentation and Test Fixtures, Smart Home and IoT Sensor Nodes.
Industrial Control Boards
The ATMEGA8535L-8JJ fits industrial control and automation boards where deterministic single-cycle RISC execution and 32 GPIO lines drive relays, contactors, and status indicators. Its three Timer/Counters with compare modes generate PWM outputs and precise event timing, while the USART connects to SCADA or HMI front ends. The 44-PLCC package is socket-compatible in many legacy industrial designs, allowing controller replacement without reflow rework. With 8 KB Flash and 512 B EEPROM, it stores calibration tables and parameter sets that survive power cycles, and the 10-bit ADC digitizes potentiometer or transducer setpoints. Maintenance of these mature boards is a primary remaining use case for this end-of-life part.
추천
Sensor Data Acquisition Systems
The integrated 8-channel 10-bit ADC makes the ATMEGA8535L-8JJ well suited to multi-sensor acquisition nodes such as temperature, pressure, and level monitoring panels. Eight single-ended analog inputs (PA0-PA7) digitize sensor channels without an external ADC, reducing BOM cost and board area, while the TWI/I2C bus expands channel count with external converters when more than eight inputs are needed. At 8 MHz the core delivers roughly 8 MIPS, sufficient to sample several channels at hundreds of samples per second with filtering. AREF/AVCC pins support precision railed analog references. Data can be streamed over USART or buffered to the 512-byte EEPROM for event logging.
추천
Legacy Embedded System Maintenance
Many installed products - metering equipment, medical accessories, and test fixtures - were designed around the ATmega8535 in 44-PLCC sockets, and the ATMEGA8535L-8JJ remains the direct maintenance component for these fleets. Because the PLCC package is socketed in most such designs, field service technicians can swap the MCU without soldering equipment. Self-programming Flash with Read-While-Write supports in-field bootloader firmware updates over the existing USART or TWI link, avoiding product recalls. Procurement teams should perform last-time-buy evaluation now given end-of-life status, or qualify the same-die TQFP variants (ATMEGA8535L-8AJ/8AU) with PLCC-to-TQFP adapters where sockets permit.
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Motor Control Auxiliaries
For brushed DC motor and stepper motor control, the ATMEGA8535L-8JJ generates PWM via its Timer/Counter compare outputs and reads feedback from current shunts or position potentiometers through the 10-bit ADC. At 8 MHz, PWM frequencies in the kilohertz range with 8-bit resolution are achievable, adequate for speed and direction control in pumps, fans, and small conveyors. The 32 GPIO lines interface to H-bridge driver ICs and limit switches. Note the device lacks complementary PWM outputs and hardware dead-time insertion, so complex three-phase drives need external logic or a newer MCU; within those limits it provides a complete, low-cost control solution.
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Instrumentation and Test Fixtures
Bench instruments and production test fixtures benefit from the ATMEGA8535L-8JJ's combination of a 10-bit ADC for measurement capture, USART for PC communication, and SPI for controlling DACs, digital potentiometers, and relay banks. The Harvard architecture executes control loops with deterministic timing, while 8 KB Flash holds test sequences and lookup tables and 512 B EEPROM stores calibration constants between calibration cycles. The 44-PLCC package fits the socketed MCU carriers common in fixture electronics. Its low-voltage L-grade operation also permits 3.3V logic interfacing with modern instruments when clocked within the low-voltage frequency envelope.
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Smart Home and IoT Sensor Nodes
The ATMEGA8535L-8JJ can serve low-power connected nodes using its wide L-grade supply range down to roughly 2.7V, allowing operation directly from three alkaline cells or a single lithium cell via LDO. The TWI (I2C) bus attaches humidity, temperature, and proximity sensors, while the 10-bit ADC reads battery voltage and analog sensors for health monitoring. Firmware can place the static core in sleep and wake on external interrupts to extend battery life. Communication to a gateway runs over the USART at up to 115.2 kbaud. For new IoT designs, newer AVRs with built-in connectivity are preferable, but this part suits maintenance and retrofit projects.
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추천 제품 요약
엔지니어링 참조 데이터: ATMEGA8535L-8JJ — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ATMEGA8535L-8JI | ATMEGA8535-16PJ | AT90S8535-8JC | ATMEGA8535L-8AJ |
|---|---|---|---|---|---|
| Package | 44-PLCC | 44-PLCC - same | 44-PLCC - same | 44-PLCC - same | 44-TQFP - different (adapter needed) |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology (Atmel legacy) | Microchip Technology |
| Max Clock Frequency | 8 MHz | 8 MHz | 16 MHz | 8 MHz | 8 MHz |
| Flash Memory | 8 KB | 8 KB | 8 KB | 8 KB | 8 KB |
| SRAM | 512 bytes | 512 bytes | 512 bytes | 512 bytes | 512 bytes |
| EEPROM | 512 bytes | 512 bytes | 512 bytes | 512 bytes | 512 bytes |
| ADC | 8-channel 10-bit | 8-channel 10-bit | 8-channel 10-bit | 8-channel 10-bit | 8-channel 10-bit |
| GPIO Count | 32 lines | 32 lines | 32 lines | 32 lines | 32 lines |
| Lifecycle Status | EOL / last-time-buy | EOL | Mature / limited availability | Obsolete | EOL |
주요 차별점
- Same-package L-grade availability (vs ATMEGA8535-16PJ)
- Self-programming Flash with Read-While-Write (vs AT90S8535-8JC)
- PLCC footprint preserved across family (vs ATMEGA8535L-8AJ)
설계 노트
Decouple VCC and AVCC separately: place a 100 nF ceramic capacitor within a few millimeters of each pin plus one 10 uF bulk capacitor per supply rail. AVCC should be connected to VCC through a low-pass LC filter (10 uH + 100 nF) when ADC accuracy matters, and AREF must be decoupled with 100 nF to ground. Estimated: with 8 MHz clock and typical I/O loading, current draw stays in the low tens of mA - well within PLCC-44 thermal capability, so no heatsinking is needed.
Do not clock the L-grade part above 8 MHz - overclocking the low-voltage grade outside its safe voltage-frequency envelope causes unreliable flash reads and brown-outs. If the design needs 16 MHz, use the standard-grade ATMEGA8535-16PJ instead. Also verify fuse settings (CKOPT, BOD level) before first programming; enabling brown-out detection around 2.7-4.0V depending on supply prevents EEPROM corruption during brown-out events, a well-documented failure mode in AVR designs.
For socketed PLCC applications, inspect socket contacts during service swaps - PLCC sockets develop intermittent contact oxidation that mimics MCU failure. Keep the analog ground return of AREF/AVCC star-connected to the main ground plane to avoid digital switching noise modulating ADC readings. Route SPI and TWI bus traces short; TWI requires 4.7 kilo-ohm pull-ups on SCL/SDA per datasheet recommendations. Reserve ISP header access on production boards since the parallel High-Voltage programming recovery path needs full pin access that sockets may block.
Clock source quality matters: a crystal with 12-22 pF load capacitors at XTAL1/XTAL2 gives the most stable 8 MHz operation, while external clock drive should use a clean square wave with rise times under 10 ns. Keep the crystal loop traces under 15 mm and guard with ground. For the ADC, sample when digital I/O activity is minimal (e.g., use ADC Noise Canceler sleep mode) - the 10-bit converter loses effective bits when switching noise couples in through AVCC.
규정 준수 정보
Compliance status not stated in the retrieved web data. Verify RoHS/REACH status on the Microchip product page or distributor certificate of conformity before order.
