ATMEGA8535L-8JJ - 8KB AVR MCU, 8MHz, 44-PLCC | Microchip
MPN: ATMEGA8535L-8JJ β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.54 | $3.54 |
| 10 | $3.35 | $33.50 |
| 100 | $3.1 | $310.00 |
| 500 | $2.9 | $1,450.00 |
| 1,000 | $2.75 | $2,750.00 |
ATMEGA8535L-8JJ Overview
An AVR microcontroller is a family of 8-bit Harvard-architecture MCUs from Microchip (originally Atmel) that executes most instructions in a single clock cycle. Within the product hierarchy, the ATmega8535 sits at: microcontroller -> 8-bit MCU -> AVR ATmega family. Because program memory and data memory are separate buses, the AVR can achieve up to 16 MIPS throughput at 16 MHz, delivering performance typically requiring larger clock speeds in CISC architectures.
Key features include 130 powerful RISC instructions (most single-cycle), 32 general-purpose working registers, 32 programmable I/O lines, and three flexible Timer/Counters with compare modes. The device also integrates a byte-oriented Two-wire Serial Interface (TWI, I2C-compatible), a serial programmable USART, an SPI interface, and internal/external interrupt sources. The 10-bit ADC resolves 8 single-ended channels, suitable for sensor interfaces in cost-sensitive designs.
The L suffix denotes the low-voltage product grade, operating from 2.7V to 5.5V with a maximum clock of 8 MHz, versus the 16 MHz standard grade. Self-programming Flash with Read-While-Write support enables field firmware updates without external programmers, while ISP via SPI simplifies production programming.
Typical applications include industrial control boards, sensor data acquisition systems, motor control auxiliaries, and legacy embedded systems where the 44-PLCC footprint must be maintained for socketed or board-level compatibility.
Designers should note the 8 MHz limit of the L-grade part: designs requiring 16 MHz throughput must use the standard-grade ATmega8535 variant instead.
This page synthesizes verified distributor pricing, drop-in alternatives, pinout details, and practical design notes beyond what the manufacturer datasheet provides.
Drop-in alternatives for ATMEGA8535L-8JJ β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ATMEGA8535L-8JJ (same form factor and footprint) β differing in Mounting Type, Package, ADC, Communication Interfaces, Core Architecture.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
ATMEGA8535L-8JI
β Drop-Inβ In Stock
$3.68 / Unit
View Datasheet βATMEGA8535-16PJ
β Drop-Inβ In Stock
$3.4 / Unit
View Datasheet βATMEGA8535-16JI
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
AT90S8535-8JC
β Drop-Inπ Reference alternative (not in catalog)
ATMEGA8535L-8JJ Maximum Ratings & Electrical Characteristics
| Core Architecture | AVR 8-bit RISC |
| Flash Program Memory | 8 KB |
| SRAM | 512 bytes |
| EEPROM | 512 bytes |
| Maximum Clock Frequency | 8 MHz |
| Maximum Throughput | Up to 16 MIPS at 16 MHz (family) |
| Instructions | 130 powerful instructions, most single-cycle |
| ADC | 8-channel, 10-bit |
| General Purpose I/O | 32 lines |
| Working Registers | 32 general purpose |
| Timers/Counters | Three flexible Timer/Counters with compare modes |
| Serial Interfaces | USART, Two-wire Serial Interface (TWI/I2C-compatible), SPI |
| Package | 44-PLCC (J) |
| Mounting Type | Surface Mount |
| Number of Pins | 44 |
| Flash Organization | 4K x 16 (self-programming, Read-While-Write) |
| In-System Programming | Yes (ISP via SPI) |
ATMEGA8535L-8JJ Pin Configuration
| Pin 1 | PA3 (ADC3) β Port A bit 3 / ADC channel 3 input |
| Pin 2 | PA4 (ADC4) β Port A bit 4 / ADC channel 4 input |
| Pin 3 | PA5 (ADC5) β Port A bit 5 / ADC channel 5 input |
| Pin 4 | PA6 (ADC6) β Port A bit 6 / ADC channel 6 input |
| Pin 5 | PA7 (ADC7) β Port A bit 7 / ADC channel 7 input |
| Pin 6 | AREF β Analog reference voltage for ADC |
| Pin 7 | AVCC β Analog supply voltage for ADC |
| Pin 8 | PB0 (SS) β Port B bit 0 / SPI Slave Select |
| Pin 9 | PB1 (T1) β Port B bit 1 / Timer1 external clock input |
| Pin 10 | PB2 (AIN0) β Port B bit 2 / Analog Comparator positive input |
| Pin 11 | PB3 (AIN1) β Port B bit 3 / Analog Comparator negative input |
| Pin 12 | PB4 (SS) β Port B bit 4 / SPI Slave Select |
| Pin 13 | PB5 (MOSI) β Port B bit 5 / SPI Master Output Slave Input |
| Pin 14 | PB6 (MISO) β Port B bit 6 / SPI Master Input Slave Output |
| Pin 15 | PB7 (SCK/OC0) β Port B bit 7 / SPI Clock or Timer0 output compare |
| Pin 16 | PC0 (SCL) β Port C bit 0 / TWI clock |
| Pin 17 | PC1 (SDA) β Port C bit 1 / TWI data |
| Pin 18 | PC2 (TCK) β Port C bit 2 / JTAG test clock |
| Pin 19 | PC3 (TMS) β Port C bit 3 / JTAG test mode select |
| Pin 20 | PC4 (TDO) β Port C bit 4 / JTAG test data out |
| Pin 21 | PC5 (TDI) β Port C bit 5 / JTAG test data in |
| Pin 22 | PC6 (TOSC1) β Port C bit 6 / Timer oscillator input |
| Pin 23 | PC7 (TOSC2) β Port C bit 7 / Timer oscillator output |
| Pin 24 | PD0 (RXD) β Port D bit 0 / USART receive |
| Pin 25 | PD1 (TXD) β Port D bit 1 / USART transmit |
| Pin 26 | PD2 (INT0) β Port D bit 2 / External interrupt 0 |
| Pin 27 | PD3 (INT1) β Port D bit 3 / External interrupt 1 |
| Pin 28 | PD4 (OC1B) β Port D bit 4 / Timer1 output compare B |
| Pin 29 | PD5 (OC1A) β Port D bit 5 / Timer1 output compare A |
| Pin 30 | PD6 (ICP1) β Port D bit 6 / Timer1 input capture |
| Pin 31 | PD7 (OC2) β Port D bit 7 / Timer2 output compare |
| Pin 32 | VCC β Digital supply voltage |
| Pin 33 | GND β Digital ground |
| Pin 34 | PA0 (ADC0) β Port A bit 0 / ADC channel 0 input |
| Pin 35 | PA1 (ADC1) β Port A bit 1 / ADC channel 1 input |
| Pin 36 | PA2 (ADC2) β Port A bit 2 / ADC channel 2 input |
| Pin 37 | PE0 (ICP3/CLKO) β Alternate-function pin (per datasheet pin configuration) |
| Pin 38 | XTAL1 β External clock input / crystal in |
| Pin 39 | XTAL2 β Crystal output / oscillator amplifier output |
| Pin 40 | RESET β Active-low reset input |
| Pin 41 | NC β Not connected (per datasheet) |
| Pin 42 | NC β Not connected (per datasheet) |
| Pin 43 | NC β Not connected (per datasheet) |
| Pin 44 | NC β Not connected (per datasheet) |
Typical Applications
ATMEGA8535L-8JJ is suitable for 6 applications: Industrial Control Boards, Sensor Data Acquisition Systems, Legacy Embedded System Maintenance, Motor Control Auxiliaries, Instrumentation and Test Fixtures, Smart Home and IoT Sensor Nodes.
Industrial Control Boards
The ATMEGA8535L-8JJ fits industrial control and automation boards where deterministic single-cycle RISC execution and 32 GPIO lines drive relays, contactors, and status indicators. Its three Timer/Counters with compare modes generate PWM outputs and precise event timing, while the USART connects to SCADA or HMI front ends. The 44-PLCC package is socket-compatible in many legacy industrial designs, allowing controller replacement without reflow rework. With 8 KB Flash and 512 B EEPROM, it stores calibration tables and parameter sets that survive power cycles, and the 10-bit ADC digitizes potentiometer or transducer setpoints. Maintenance of these mature boards is a primary remaining use case for this end-of-life part.
Recommended
Sensor Data Acquisition Systems
The integrated 8-channel 10-bit ADC makes the ATMEGA8535L-8JJ well suited to multi-sensor acquisition nodes such as temperature, pressure, and level monitoring panels. Eight single-ended analog inputs (PA0-PA7) digitize sensor channels without an external ADC, reducing BOM cost and board area, while the TWI/I2C bus expands channel count with external converters when more than eight inputs are needed. At 8 MHz the core delivers roughly 8 MIPS, sufficient to sample several channels at hundreds of samples per second with filtering. AREF/AVCC pins support precision railed analog references. Data can be streamed over USART or buffered to the 512-byte EEPROM for event logging.
Recommended
Legacy Embedded System Maintenance
Many installed products - metering equipment, medical accessories, and test fixtures - were designed around the ATmega8535 in 44-PLCC sockets, and the ATMEGA8535L-8JJ remains the direct maintenance component for these fleets. Because the PLCC package is socketed in most such designs, field service technicians can swap the MCU without soldering equipment. Self-programming Flash with Read-While-Write supports in-field bootloader firmware updates over the existing USART or TWI link, avoiding product recalls. Procurement teams should perform last-time-buy evaluation now given end-of-life status, or qualify the same-die TQFP variants (ATMEGA8535L-8AJ/8AU) with PLCC-to-TQFP adapters where sockets permit.
Recommended
Motor Control Auxiliaries
For brushed DC motor and stepper motor control, the ATMEGA8535L-8JJ generates PWM via its Timer/Counter compare outputs and reads feedback from current shunts or position potentiometers through the 10-bit ADC. At 8 MHz, PWM frequencies in the kilohertz range with 8-bit resolution are achievable, adequate for speed and direction control in pumps, fans, and small conveyors. The 32 GPIO lines interface to H-bridge driver ICs and limit switches. Note the device lacks complementary PWM outputs and hardware dead-time insertion, so complex three-phase drives need external logic or a newer MCU; within those limits it provides a complete, low-cost control solution.
Recommended
Instrumentation and Test Fixtures
Bench instruments and production test fixtures benefit from the ATMEGA8535L-8JJ's combination of a 10-bit ADC for measurement capture, USART for PC communication, and SPI for controlling DACs, digital potentiometers, and relay banks. The Harvard architecture executes control loops with deterministic timing, while 8 KB Flash holds test sequences and lookup tables and 512 B EEPROM stores calibration constants between calibration cycles. The 44-PLCC package fits the socketed MCU carriers common in fixture electronics. Its low-voltage L-grade operation also permits 3.3V logic interfacing with modern instruments when clocked within the low-voltage frequency envelope.
Recommended
Smart Home and IoT Sensor Nodes
The ATMEGA8535L-8JJ can serve low-power connected nodes using its wide L-grade supply range down to roughly 2.7V, allowing operation directly from three alkaline cells or a single lithium cell via LDO. The TWI (I2C) bus attaches humidity, temperature, and proximity sensors, while the 10-bit ADC reads battery voltage and analog sensors for health monitoring. Firmware can place the static core in sleep and wake on external interrupts to extend battery life. Communication to a gateway runs over the USART at up to 115.2 kbaud. For new IoT designs, newer AVRs with built-in connectivity are preferable, but this part suits maintenance and retrofit projects.
Recommended
Recommended Products Summary
Engineering reference data for ATMEGA8535L-8JJ β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ATMEGA8535L-8JI | ATMEGA8535-16PJ | AT90S8535-8JC | ATMEGA8535L-8AJ |
|---|---|---|---|---|---|
| Package | 44-PLCC | 44-PLCC - same | 44-PLCC - same | 44-PLCC - same | 44-TQFP - different (adapter needed) |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology (Atmel legacy) | Microchip Technology |
| Max Clock Frequency | 8 MHz | 8 MHz | 16 MHz | 8 MHz | 8 MHz |
| Flash Memory | 8 KB | 8 KB | 8 KB | 8 KB | 8 KB |
| SRAM | 512 bytes | 512 bytes | 512 bytes | 512 bytes | 512 bytes |
| EEPROM | 512 bytes | 512 bytes | 512 bytes | 512 bytes | 512 bytes |
| ADC | 8-channel 10-bit | 8-channel 10-bit | 8-channel 10-bit | 8-channel 10-bit | 8-channel 10-bit |
| GPIO Count | 32 lines | 32 lines | 32 lines | 32 lines | 32 lines |
| Lifecycle Status | EOL / last-time-buy | EOL | Mature / limited availability | Obsolete | EOL |
Key Differentiators
- Same-package L-grade availability (vs ATMEGA8535-16PJ)
- Self-programming Flash with Read-While-Write (vs AT90S8535-8JC)
- PLCC footprint preserved across family (vs ATMEGA8535L-8AJ)
Design Notes
Decouple VCC and AVCC separately: place a 100 nF ceramic capacitor within a few millimeters of each pin plus one 10 uF bulk capacitor per supply rail. AVCC should be connected to VCC through a low-pass LC filter (10 uH + 100 nF) when ADC accuracy matters, and AREF must be decoupled with 100 nF to ground. Estimated: with 8 MHz clock and typical I/O loading, current draw stays in the low tens of mA - well within PLCC-44 thermal capability, so no heatsinking is needed.
Do not clock the L-grade part above 8 MHz - overclocking the low-voltage grade outside its safe voltage-frequency envelope causes unreliable flash reads and brown-outs. If the design needs 16 MHz, use the standard-grade ATMEGA8535-16PJ instead. Also verify fuse settings (CKOPT, BOD level) before first programming; enabling brown-out detection around 2.7-4.0V depending on supply prevents EEPROM corruption during brown-out events, a well-documented failure mode in AVR designs.
For socketed PLCC applications, inspect socket contacts during service swaps - PLCC sockets develop intermittent contact oxidation that mimics MCU failure. Keep the analog ground return of AREF/AVCC star-connected to the main ground plane to avoid digital switching noise modulating ADC readings. Route SPI and TWI bus traces short; TWI requires 4.7 kilo-ohm pull-ups on SCL/SDA per datasheet recommendations. Reserve ISP header access on production boards since the parallel High-Voltage programming recovery path needs full pin access that sockets may block.
Clock source quality matters: a crystal with 12-22 pF load capacitors at XTAL1/XTAL2 gives the most stable 8 MHz operation, while external clock drive should use a clean square wave with rise times under 10 ns. Keep the crystal loop traces under 15 mm and guard with ground. For the ADC, sample when digital I/O activity is minimal (e.g., use ADC Noise Canceler sleep mode) - the 10-bit converter loses effective bits when switching noise couples in through AVCC.
Compliance Information
Compliance status not stated in the retrieved web data. Verify RoHS/REACH status on the Microchip product page or distributor certificate of conformity before order.
