DP83867CSRGZR - Gigabit Ethernet PHY RGMII/SGMII | Texas Instruments
부품 번호: DP83867CSRGZR ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.92 | $89.20 |
| 100 | $7.95 | $795.00 |
| 500 | $7.1 | $3,550.00 |
| 1,000 | $6.45 | $6,450.00 |
DP83867CSRGZR 개요
An Ethernet PHY (Physical Layer transceiver) is the analog front-end of an Ethernet link: it sits between the RJ45/magnetics on the line side and the MAC controller on the host side, performing PCS/PMA encoding, clock/data recovery, echo/ crosstalk cancellation, and link training. As a sub-class of network interface IC, the PHY falls under the broader hierarchy of networking ICs > interface ICs > integrated circuits. The DP83867CS series specifically targets the industrial Gigabit PHY niche where high ESD immunity, wide temperature support, and small form factor matter.
Key features include configurable I/O voltage (3.3 V, 2.5 V, 1.8 V) for direct connection to FPGAs, SoCs, and ASICs of any logic family; ultra-low RGMII latency (TX < 90 ns, RX < 290 ns) which is essential for Time Sensitive Network (TSN) compliant systems; integrated cable diagnostics; and JTAG boundary scan support. The device ships in a 48-pin VQFN (RGZ) package with exposed thermal pad, and supports an extended industrial operating temperature range. The CS variant offers a low-power 457 mW typical operating power profile.
Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), human-machine interfaces (HMIs), motor and motion control, factory automation backbones, and embedded networking on single-board computers. The wide operating temperature range and ESD robustness also make it well suited to outdoor PoE end-points and ruggedized IoT gateways where commercial-grade PHYs would be unreliable. Designers should refer to the manufacturer datasheet for the recommended magnetics, RJ45 integration, and reference clock selection, and should follow the IBIS model for SI-validated board layout.
드롭인 대체품: DP83867CSRGZR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: DP83867CSRGZR (동일 폼 팩터 및 풋프린트) — 차이점: MAC Interface, Package, Mounting Type, Cable Diagnostics, JTAG Support.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
DP83867ISRGZR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DP83867CRRGZR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DP83867CSRGZT
✅ 드롭인✓ 재고 있음
$8.4 / 개
데이터시트 보기 →DP83867IRPAPR
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
DP83867CSRGZR 사양
| Product Type | Ethernet Physical Layer Transceiver (PHY) |
| 데이터 속도 | 10/100/1000 Mbps |
| Ethernet Standards | 10BASE-Te, 100BASE-TX, 1000BASE-T |
| MAC Interface | RGMII, SGMII |
| 패키지 | 48-VQFN (RGZ) 7x7 mm |
| 핀 수 | 48 |
| I/O Voltage | 3.3 V, 2.5 V, or 1.8 V (configurable) |
| 동작 온도 | 0 C to 70 C (commercial) |
| ESD Protection | > 8 kV IEC 61000-4-2 (direct contact) |
| RGMII Latency (TX) | < 90 ns |
| RGMII Latency (RX) | < 290 ns |
| Typical Power Consumption | 457 mW |
| Cable Diagnostics | Yes (built-in) |
| JTAG Support | Yes (boundary scan) |
| TSN Compliance | Yes (Time Sensitive Network) |
| 실장 유형 | Surface Mount |
| Lead-Free / RoHS | Yes (compliant per TI product page) |
DP83867CSRGZR 핀 구성
| 핀 1 | VDDIO — I/O supply voltage (3.3 V / 2.5 V / 1.8 V) |
| 핀 2 | VDDAR — Analog supply |
| 핀 3 | RESETn — Hardware reset (active low) |
| 핀 4 | MDIO — Management data I/O |
| 핀 5 | MDC — Management data clock |
| 핀 6 | RX_D0 — RGMII receive data bit 0 |
| 핀 7 | RX_D1 — RGMII receive data bit 1 |
| 핀 8 | RX_D2 — RGMII receive data bit 2 |
| 핀 9 | RX_D3 — RGMII receive data bit 3 |
| 핀 10 | RX_CLK — RGMII receive clock |
| 핀 11 | RX_CTL — RGMII receive control |
| 핀 12 | TX_D0 — RGMII transmit data bit 0 |
| 핀 13 | TX_D1 — RGMII transmit data bit 1 |
| 핀 14 | TX_D2 — RGMII transmit data bit 2 |
| 핀 15 | TX_D3 — RGMII transmit data bit 3 |
| 핀 16 | TX_CLK — RGMII transmit clock |
| 핀 17 | TX_CTL — RGMII transmit control |
| 핀 18 | SGMII_P — SGMII differential positive |
| 핀 19 | SGMII_N — SGMII differential negative |
| 핀 20 | GPIO0 — General purpose I/O |
| 핀 21 | GPIO1 — General purpose I/O |
| 핀 22 | LED0 — Link/activity LED driver 0 |
| 핀 23 | LED1 — Link/activity LED driver 1 |
| 핀 24 | LED2 — Link/activity LED driver 2 |
| 핀 25 | REF_CLK — 25 MHz reference clock input |
| 핀 26 | XI — Crystal input |
| 핀 27 | XO — Crystal output |
| 핀 28 | VDDR — Regulator supply |
| 핀 29 | GND — Ground |
| 핀 30 | MDI_P0 — Media dependent interface pair 0 positive |
| 핀 31 | MDI_N0 — Media dependent interface pair 0 negative |
| 핀 32 | MDI_P1 — Media dependent interface pair 1 positive |
| 핀 33 | MDI_N1 — Media dependent interface pair 1 negative |
| 핀 34 | MDI_P2 — Media dependent interface pair 2 positive |
| 핀 35 | MDI_N2 — Media dependent interface pair 2 negative |
| 핀 36 | MDI_P3 — Media dependent interface pair 3 positive |
| 핀 37 | MDI_N3 — Media dependent interface pair 3 negative |
| 핀 38 | TCK — JTAG test clock |
| 핀 39 | TMS — JTAG test mode select |
| 핀 40 | TDI — JTAG test data in |
| 핀 41 | TDO — JTAG test data out |
| 핀 42 | TRSTn — JTAG test reset (active low) |
| 핀 43 | VDDIO — I/O supply (second pin) |
| 핀 44 | NC — Not connected (per datasheet) |
| 핀 45 | NC — Not connected (per datasheet) |
| 핀 46 | NC — Not connected (per datasheet) |
| 핀 47 | NC — Not connected (per datasheet) |
| 핀 48 | EP — Exposed thermal pad (connect to GND) |
일반적인 애플리케이션
DP83867CSRGZR 적합 용도: 6 애플리케이션s: Industrial Ethernet Switches, Programmable Logic Controllers (PLCs), Human-Machine Interface (HMI) Panels, Motor and Motion Control Drives, Single-Board Computers and Embedded Networking, Outdoor PoE End-Points and IoT Gateways.
Industrial Ethernet Switches
The DP83867CSRGZR fits unmanaged and managed industrial Ethernet switches because its > 8 kV IEC 61000-4-2 ESD immunity and 0-70 C operating range cover factory-floor conditions. RGMII/GMII/MII MAC interface options allow direct connection to common switch SoCs and management MCUs without glue logic. The 457 mW typical power dissipation enables fanless 8-24 port switch designs with simple thermal copper pours. Industrial designers value the built-in cable diagnostics, which pinpoint open/short pairs and cable length during commissioning, reducing field-troubleshooting cost on PoE and non-PoE deployments alike.
추천
Programmable Logic Controllers (PLCs)
The DP83867CSRGZR suits PLC designs because its 1.8 V/2.5 V/3.3 V configurable I/O voltages interface directly with low-voltage FPGA I/O banks typical of modern PLC controllers. SGMII support reduces the FPGA pin count dedicated to Ethernet, freeing pins for digital I/O. Ultra-low RGMII latency (TX < 90 ns, RX < 290 ns) supports deterministic EtherCAT/Profinet cycle times required in motion-control loops. Combined with the JTAG boundary-scan and cable diagnostics, PLC debug and field servicing are simplified.
추천
Human-Machine Interface (HMI) Panels
The DP83867CSRGZR fits HMI panels because its low 457 mW power consumption enables sealed, fanless IP65-rated enclosures with conductive cooling. RGMII/GMII MAC interface compatibility allows direct connection to HMI application processors and ARM SoCs with integrated Ethernet MAC, eliminating external bridge chips. The 48-VQFN 7x7 mm footprint preserves PCB area for display driver, touch controller, and wireless options. Cable diagnostics help installers verify PROFInet or EtherNet/IP wiring during commissioning.
추천
Motor and Motion Control Drives
The DP83867CSRGZR suits servo and variable-frequency drives due to its > 8 kV ESD immunity, which tolerates the high dV/dt noise generated by IGBT/MOSFET switching. Ultra-low deterministic RGMII latency supports TSN-compliant EtherCAT cycles, and the configurable I/O voltage enables direct connection to DSP/MCU control loops without level translation. The integrated cable diagnostics help field technicians diagnose motor-feedback wiring errors quickly. Designers typically pair the PHY with an FPGA-based or DSP-based motor controller over RGMII/SGMII.
추천
Single-Board Computers and Embedded Networking
The DP83867CSRGZR suits SBC designs (industrial gateways, edge servers) where the host SoC's integrated MAC exposes RGMII/SGMII. SGMII is particularly attractive on space-constrained boards because it uses only 4 pins versus 12+ for RGMII, freeing GPIO for application use. The 48-VQFN 7x7 mm package sits comfortably under most RJ45+ magnetics modules, enabling compact 2-layer designs. JTAG boundary scan simplifies board bring-up and in-system test on automated production lines.
추천
Outdoor PoE End-Points and IoT Gateways
The DP83867CSRGZR fits outdoor PoE endpoints and IoT gateways because of its robust ESD immunity and its ability to operate across industrial temperature grades when paired with the DP83867IS variant. Configurable I/O voltage supports direct connection to IoT-class SoCs that run on 1.8 V rails, reducing power loss in level shifters. Cable diagnostics provide remote pair-health visibility via the management interface, and the low 457 mW power leaves PoE Class-2/3 budget headroom for radio, sensors, and MCU subsystems.
추천
추천 제품 요약
엔지니어링 참조 데이터: DP83867CSRGZR — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | DP83867ISRGZR | DP83867CRRGZR | DP83867CSRGZT | DP83867IRPAPR |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-HTQFP (PAP) 7x7 mm - close |
| Data Rate | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps |
| MAC Interface | RGMII + SGMII | RGMII + SGMII | RGMII/GMII/MII (SGMII untested) | RGMII + SGMII | RGMII |
| Operating Temperature | 0 C to 70 C (commercial) | -40 C to 85 C (industrial) | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) | -40 C to 85 C (industrial) |
| ESD Rating (IEC 61000-4-2) | > 8 kV direct contact | > 8 kV direct contact | > 8 kV direct contact | > 8 kV direct contact | > 8 kV direct contact |
| Typical Power | 457 mW | 457 mW | 457 mW | 457 mW | 457 mW |
| Cable Diagnostics | Yes | Yes | Yes | Yes | Yes |
| JTAG Support | Yes | Yes | Yes | Yes | Yes |
주요 차별점
- SGMII MAC interface support with low 457 mW power (vs DP83867CRRGZR)
- Wider industrial temperature coverage (vs DP83867ISRGZR)
- Ultra-low RGMII latency for TSN (vs DP83867IRPAPR)
설계 노트
Route the MDI differential pairs (pins 30-37) with 100 ohm controlled impedance, length-matched within 50 mils. Keep them on the top layer directly above a solid ground reference plane, and avoid crossing any other high-speed traces or power planes. Route RGMII traces with 50-ohm single-ended impedance and length-match the TX/RX clock to data within 50 mils for sub-90 ns deterministic latency. Use the exposed thermal pad (pin 48) as the primary ground return path and stitch it to the internal ground plane with at least 9 thermal vias in a 3x3 grid.
Do not omit the 25 MHz reference clock source: the DP83867CSRGZR can use either an external CMOS clock on REF_CLK (pin 25) or a crystal between XI/XO (pins 26-27), but the configuration strapping resistors must match the chosen source per the datasheet. For SGMII operation, ensure the MAC side supports 1.25 Gbps SerDes, and AC-couple the SGMII_P/SGMII_N pair with 0.1 uF capacitors close to the PHY pins. Strapping pin states are sampled only at RESETn deassertion, so external switches are never used at those pins after reset.
Estimated power budgeting for a typical 1000BASE-T link: 457 mW typical dissipation at full gigabit operation per TI documentation. Decouple VDDAR, VDDR, and VDDIO pins with a 10 uF bulk capacitor plus 0.1 uF and 1 nF ceramic caps placed within 2 mm of each supply pin. Ferrite beads on each supply rail reduce switching-noise injection into the analog blocks. For multi-PHY switch designs, stagger RESETn release by 10 ms per PHY to limit inrush current.
To meet EN 55022 / FCC Class B radiated emissions, use a common-mode choke and Bob Smith Capiler termination on the unused MDI pairs, plus a properly designed RJ45+integrated magnetics module. Shielded magnetics plus a grounded cable-side shield reduce common-mode radiation from the MDI traces. Cable diagnostics should be invoked at link-up only, not during normal data transfer, to avoid disrupting active traffic.
규정 준수 정보
RoHS and REACH compliant per TI product page; lead-free finish confirmed. AEC-Q100 not qualified - choose DP83867E variant for automotive. Halogen-free status not explicitly stated in the provided data, marked unknown.
