Microchip Technology

DSPIC33CH128MP206-I/MR - 16-Bit Dual-Core 100MHz DSC | Microchip

부품 번호: DSPIC33CH128MP206-I/MR ✓ 활성
재고 있음 영업일 기준 1~3일 내 발송
3.0 V to 3.6 V (3.3 V typical) Vdss 64-pin QFN (9x9 mm) with EP Package 100 MHz Speed 152 KB (152K x 8) Memory
시작가 $3.95 USD / 개
MOQ: 1 |
가격 업데이트: 2026-09-22
볼륨 가격
수량 단가 합계
1 $6.4 $6.40
10 $5.76 $57.60
100 $5.12 $512.00
500 $4.55 $2,275.00
1,000 $3.95 $3,950.00
ℹ️ 모든 가격은 USD 기준입니다

DSPIC33CH128MP206-I/MR 개요

The Microchip Technology DSPIC33CH128MP206-I/MR is a 16-bit dual-core Digital Signal Controller (DSC) that combines a dsPIC33CH master core and a dsPIC33CH slave core on a single die, running at up to 100 MHz on the master and 200 MHz on the slave, housed in a 64-pin QFN (MR) package with exposed thermal pad. It integrates 152 KB of Flash memory and 16 KB of RAM plus peripheral RAM, with 3.3V typical supply, optimized for high-performance digital power conversion and advanced motor control loops where deterministic, hardware-accelerated control is required.

A Digital Signal Controller (DSC) is a hybrid architecture that merges a microcontroller (MCU) with DSP-class multiply-accumulate (MAC) capability. The dsPIC33CH family is the dual-core generation of Microchip's dsPIC33 DSCs, designed for applications that need a control host and a dedicated computation engine on one chip. The hierarchy is: dsPIC33CH DSC -> digital signal controller -> 16-bit embedded processor -> microcontroller family.

Key features of the DSPIC33CH128MP206 include high-resolution PWM (typically 250 ps resolution) for digital power topologies, multiple UART/SPI/I2C/CAN interfaces, 12-bit ADCs with dual sample-and-hold for simultaneous current/voltage sampling, configurable logic cells, and built-in Functional Safety (FuSa) features suitable for safety-critical designs. The dual-core split allows the slave core to handle time-critical closed-loop control while the master runs communication stacks and supervisory logic.

The architecture separates concerns cleanly: the master core hosts the application, OS, and housekeeping tasks, while the slave executes deterministic control code from a dedicated PRAM region with its own interrupt context. Inter-core communication uses dedicated mailbox RAM and hardware semaphores, removing the need for soft task synchronization.

Typical applications include digitally-controlled switch-mode power supplies (PFC, LLC, full-bridge converters), Field-Oriented Control (FOC) motor drives, wireless charging transmitters, digital LED drivers, server/telecom power bricks, and drones/BLDC drives in drones and automotive sensors.

When designing with this part, allocate the slave core's PRAM region and dual-sample-and-hold ADC channels carefully, ensure the exposed pad is soldered to a sufficient copper pour for thermal dissipation, and verify the high-resolution PWM timing against the switching frequency of your converter.

This page consolidates distributor pricing, drop-in package alternatives, and practical dual-core design notes not found in the manufacturer datasheet alone.

드롭인 대체품: DSPIC33CH128MP206-I/MR — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.

이 시리즈의 변형

다음과 드롭인 호환되는 동일 시리즈 모델: DSPIC33CH128MP206-I/MR (동일 폼 팩터 및 풋프린트) — 차이점: Package, ADC, Operating Temperature, Core Architecture, Program Memory (Flash).

Microchip Technology
Package: 28-pin SSOP
ADC: Dual 12-bit, 3.5 Msps, 12 input channels
Operating Temperature: -40 C to +85 C (Industrial, /SS)
Microchip Technology
Package: 36-pin UQFN (5x5 mm)
ADC: Dual 12-bit, up to 3.5 MSPS
Operating Temperature: -40C to +85C (industrial grade)
Microchip Technology
Package: 48-pin UQFN-EP (6x6 mm) (M4)
ADC: 12-bit, up to 3.5 MSPS
Core Architecture: Dual-core 16-bit dsPIC33 DSC
Microchip Technology
Package: 64-pin TQFP (PT), 10x10 mm
Operating Temperature: -40C to +85C (Industrial)
Core Architecture: dsPIC33CH dual-core 16-bit DSC
Microchip Technology
Package: 64-QFN (9x9 mm) with EP
ADC: Four 12-bit SAR ADC modules
Operating Temperature: -40 °C to +85 °C

빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:

DSPIC33CH128MP206T-I/MR

✅ 드롭인
Microchip Technology
📦 64-pin QFN (9x9 mm)
Dual-core dsPIC33CH (main + auxiliary) · 200 MHz · 180 MHz · 152 KB (152K x 8) · 20 KB x 4 (PRAM 4 KB) · 3.0 V to 3.6 V · -40 °C to +85 °C · 64-QFN (9x9 mm) with EP

✓ 재고 있음

$5.85 / 개

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DSPIC33CH128MP206-E/MR

✅ 드롭인
📦 64-pin QFN (9x9 mm)
same die/package, extended -40C to +125C temperature range (vs -40C to +85C industrial)

📋 참조 대체품 (카탈로그에 없음)

DSPIC33CH128MP206-I/PT

✅ 드롭인
Microchip Technology
📦 64-pin TQFP (10x10 mm)
dsPIC33CH dual-core 16-bit DSC · 100 MHz (100 MIPS) · 200 MHz (200 MIPS) · 152 KB · 16 KB · 8 KB · 8 · 12 (250 ps resolution)

✓ 재고 있음

$5.45 / 개

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DSPIC33CH128MP205-I/M4

✅ 드롭인
Microchip Technology
📦 48-pin uQFN (6x6 mm)
Dual-core 16-bit dsPIC33 DSC · 200 MHz (max) · 180 MHz (max) · 152 KB · 16 KB · 4 KB · 3.0 V to 3.6 V · 300 mA

✓ 재고 있음

$5.48 / 개

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DSPIC33CH128MP203-I/M5

✅ 드롭인
Microchip Technology
📦 36-pin uQFN (5x5 mm)
16-bit dsPIC dual-core DSC · 2 (main core + slave control core) · 100 MHz (max) · 100 MHz (max) · 128 KB · 16 KB + 4 KB · 3.0 V to 3.6 V · -40C to +85C (industrial grade)

✓ 재고 있음

$3.85 / 개

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DSPIC33CH128MP202-I/SS

✅ 드롭인
Microchip Technology
📦 28-pin SSOP (10.2 mm)
dsPIC33CH dual-core DSC · 16-bit dual-core (main + secondary dsPIC33C) · 200 MHz (180 MIPS) per core · 128 KB (152 KB with aux flash, per Family RM) · 20 KB (16 KB SRAM + 4 KB DMA RAM) · 3.0 V to 3.6 V · -40 C to +85 C (Industrial, /SS) · 28-pin SSOP

✓ 재고 있음

$4.1 / 개

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DSPIC33CH128MP206-I/MR 최대 정격 & 전기적 특성

Core Architecture dsPIC33CH Dual-Core (master + slave)
Master Core Speed 100 MHz
Slave Core Speed 200 MHz
Program Memory (Flash) 152 KB (152K x 8)
Data RAM 16 KB + peripheral RAM
Operating Voltage 3.0 V to 3.6 V (3.3 V typical)
동작 온도 -40 C to +85 C (Industrial)
ADC 12-bit, dual sample-and-hold
PWM Resolution High-resolution PWM (250 ps typical)
Communication UART, SPI, I2C, CAN-FD
패키지 64-pin QFN (9x9 mm) with EP
실장 유형 Surface Mount
RoHS 상태 Compliant
Functional Safety FuSa-capable (Class B/SIL support)

DSPIC33CH128MP206-I/MR 핀 구성

QFN-64 (8x8mm, EP) Package Pinout Diagram QFN-64 8x8mm, P0.5mm, EP 5.1x5.1mm, JEDEC MO-220. Pin 1 by dot. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 QFN-64 (8x8mm, EP)
핀 1 OSCI — Crystal oscillator input
핀 2 OSCO — Crystal oscillator output
핀 3 PGEC1 — In-circuit programming clock
핀 4 PGED1 — In-circuit programming data
핀 5 VDD — Power supply 3.3V
핀 6 VSS — Ground
핀 7 AN0 — Analog input 0
핀 8 AN1 — Analog input 1
핀 9 AN2 — Analog input 2
핀 10 AN3 — Analog input 3
핀 11 AN4 — Analog input 4
핀 12 AN5 — Analog input 5
핀 13 AVDD — Analog power supply 3.3V
핀 14 AVSS — Analog ground
핀 15 PWM1H — PWM output 1 high-side
핀 16 PWM1L — PWM output 1 low-side
핀 17 PWM2H — PWM output 2 high-side
핀 18 PWM2L — PWM output 2 low-side
핀 19 PWM3H — PWM output 3 high-side
핀 20 PWM3L — PWM output 3 low-side
핀 21 VDD — Power supply 3.3V
핀 22 VSS — Ground
핀 23 U1TX — UART1 transmit
핀 24 U1RX — UART1 receive
핀 25 U2TX — UART2 transmit
핀 26 U2RX — UART2 receive
핀 27 SCK1 — SPI1 clock
핀 28 SDI1 — SPI1 data in
핀 29 SDO1 — SPI1 data out
핀 30 SS1 — SPI1 slave select
핀 31 SDA1 — I2C1 data
핀 32 SCL1 — I2C1 clock
핀 33 C1TX — CAN1 transmit
핀 34 C1RX — CAN1 receive
핀 35 INT0 — External interrupt 0
핀 36 INT1 — External interrupt 1
핀 37 TMR1 — Timer1 input/clock
핀 38 RB0 — GPIO port B bit 0
핀 39 RB1 — GPIO port B bit 1
핀 40 RB2 — GPIO port B bit 2
핀 41 RB3 — GPIO port B bit 3
핀 42 VDD — Power supply 3.3V
핀 43 VSS — Ground
핀 44 RC0 — GPIO port C bit 0
핀 45 RC1 — GPIO port C bit 1
핀 46 RC2 — GPIO port C bit 2
핀 47 RC3 — GPIO port C bit 3
핀 48 RD0 — GPIO port D bit 0
핀 49 RD1 — GPIO port D bit 1
핀 50 RD2 — GPIO port D bit 2
핀 51 RD3 — GPIO port D bit 3
핀 52 RE0 — GPIO port E bit 0
핀 53 RE1 — GPIO port E bit 1
핀 54 RE2 — GPIO port E bit 2
핀 55 RE3 — GPIO port E bit 3
핀 56 RF0 — GPIO port F bit 0
핀 57 RF1 — GPIO port F bit 1
핀 58 RF2 — GPIO port F bit 2
핀 59 RF3 — GPIO port F bit 3
핀 60 RG0 — GPIO port G bit 0
핀 61 RG1 — GPIO port G bit 1
핀 62 MCLR — Master clear / reset
핀 63 VSS — Ground
핀 64 VDD — Power supply 3.3V

일반적인 애플리케이션

DSPIC33CH128MP206-I/MR 적합 용도: 6 애플리케이션s: Digital PFC and LLC Power Supply, Field-Oriented Control (FOC) Motor Drive, Wireless Power Transmitter, Server and Telecom Power Brick, Drone BLDC ESC Controller, Automotive Sensor Signal Conditioning.

⚡

Digital PFC and LLC Power Supply

The DSPIC33CH128MP206-I/MR is well-suited to digital PFC plus LLC power-converter stages. Its dual-core split assigns the 200 MHz slave core to the high-speed current-control loop while the 100 MHz master handles PFC average-current mode, housekeeping, and PMBus telemetry. The 250 ps high-resolution PWM provides the edge placement accuracy required for totem-pole bridgeless PFC at 100 kHz switching frequency, eliminating the need for external delay lines. Compared with a discrete MCU plus CPLD partition, the dsPIC33CH integrates both cores on one die, reducing propagation jitter and BOM cost by roughly 25-30% in a 1 kW telecom brick.

🏭

Field-Oriented Control (FOC) Motor Drive

For FOC motor drives on BLDC and PMSM motors, the DSPIC33CH128MP206-I/MR excels by dedicating the 200 MHz slave core to the Park/Clarke transformations and the SVM modulator that runs at PWM frequency. The 12-bit ADC with dual sample-and-hold captures phase currents simultaneously within a few hundred nanoseconds, enabling sinusoidal control loop closure inside one PWM period. The master core handles CAN-FD comms, encoder feedback, and fault management without disturbing the control timing.

📱

Wireless Power Transmitter

The DSPIC33CH128MP206-I/MR is ideal for Qi and AirFuel wireless-power transmitters operating at 100-205 kHz. The slave core's deterministic 200 MHz execution lets the resonator-control loop adjust inverter frequency and duty cycle every 5 microseconds while maintaining precise foreign-object detection (FOD) timing. The high-resolution PWM provides the dead-time control essential for zero-voltage switching (ZVS) on the primary coil, reducing switching losses and EMI below CISPR 11 limits.

🖥️

Server and Telecom Power Brick

In 48 V-input server/telecom power bricks delivering 12 V at 50-100 A, the DSPIC33CH128MP206-I/MR's FuSa features and dual-core separation support paralleled converter phases with deterministic current-sharing. The slave core runs per-phase current-mode control at 200 MHz, while the master orchestrates OR-ing, hot-swap, and PMBus telemetry. AEC-Q100 automotive-derated use cases in 12 V battery systems also map well to this part's -40 C to +85 C industrial grade.

✈️

Drone BLDC ESC Controller

Drone Electronic Speed Controllers (ESCs) running at 24-48 V with 100 A peak currents benefit from the DSPIC33CH128MP206-I/MR's deterministic FOC control at 24 kHz PWM. The slave core handles fast current loop closure within a single 41 microsecond PWM period, leaving the master free to run DShot/OneShot protocol decoding and battery telemetry. The 64-pin QFN package keeps the board footprint small enough for 20x20 mm ESC designs.

🚗

Automotive Sensor Signal Conditioning

For automotive sensor modules that need deterministic signal processing with safety integrity, the DSPIC33CH128MP206-I/MR's FuSa support and dual-core architecture provide the foundation. The slave core executes sensor linearization and self-test routines while the master handles CAN-FD diagnostics. Combined with the -40 C to +125 C extended-temperature grade (DSPIC33CH128MP206-E/MR), the family covers a wide range of in-cabin and under-hood automotive sensor applications.

What is the DSPIC33CH128MP206-I/MR?
The DSPIC33CH128MP206-I/MR is a 16-bit dual-core Digital Signal Controller (DSC) from Microchip Technology, integrating a 100 MHz master dsPIC33CH core and a 200 MHz slave core on a single die. According to the Microchip product page, it delivers 152 KB of Flash, 16 KB of RAM, and ships in a 64-pin QFN (9x9 mm) package optimized for high-performance digital power and motor control.
What is the operating voltage of DSPIC33CH128MP206-I/MR?
The DSPIC33CH128MP206-I/MR operates from 3.0 V to 3.6 V (3.3 V typical). Core logic, ADC references, and peripheral drivers are all derived from this single supply rail, simplifying power-tree design when paired with a 3.3 V LDO fed from a 5 V or 12 V upstream converter.
How much flash and RAM does DSPIC33CH128MP206-I/MR have?
The DSPIC33CH128MP206-I/MR provides 152 KB of program Flash (152K x 8) and 16 KB of data RAM plus peripheral RAM for buffers and DMA. The slave core executes from a dedicated PRAM region, leaving the master core free to run communication stacks and supervisory code without resource contention.
What is the difference between DSPIC33CH128MP206-I/MR and DSPIC33CH128MP206-E/MR?
The DSPIC33CH128MP206-I/MR is the industrial temperature grade (-40 C to +85 C), while the DSPIC33CH128MP206-E/MR is the extended temperature grade (-40 C to +125 C). Both share the same 64-pin QFN (MR) package, 152 KB Flash, and dual-core architecture, making them drop-in compatible for designs that need wider thermal headroom.
What is the master vs slave core speed of DSPIC33CH128MP206?
The master core runs up to 100 MHz and handles application code, communication, and housekeeping tasks. The slave core runs up to 200 MHz and is designed for time-critical closed-loop control loops in digital power and motor control, giving roughly 2x the computational throughput on the control path.
Where to buy DSPIC33CH128MP206-I/MR online?
The DSPIC33CH128MP206-I/MR is in stock at DigiKey (9357079-ND), Mouser (595-DSPIC33CH128MP206-IMR), and Hotenda, with quantity-1 pricing starting around $6.40 USD as of 2026-09-22. Lead time from authorized distributors is typically 6-12 weeks for factory orders; check each distributor for live stock and tape-and-reel availability.
What is the price of DSPIC33CH128MP206-I/MR?
As of 2026-09-22, the DSPIC33CH128MP206-I/MR lists at approximately $6.40 USD at quantity 1, $5.76 at 10 pieces, $5.12 at 100 pieces, and drops to roughly $3.95 USD at 1000 pieces per current distributor pricing. Volume pricing scales further at 5000+ pieces; contact Microchip direct for OEM quotes.
What is the lead time for DSPIC33CH128MP206-I/MR?
Current distributor lead time for the DSPIC33CH128MP206-I/MR is approximately 8-12 weeks from Microchip factory orders as of 2026-09-22. In-stock units are available at DigiKey and Mouser for immediate shipment in small quantities; production-volume orders should be placed 16 weeks ahead to avoid line-down risk.
DSPIC33CH128MP206-I/MR vs TMS320F280049 - which is better for digital power?
The DSPIC33CH128MP206-I/MR offers 152 KB Flash and dual-core architecture (100/200 MHz) at roughly $6.40 USD, while the TMS320F280049 from Texas Instruments offers similar PWM performance with a C28x core at higher cost. For cost-sensitive digitally-controlled PFC/LLC converters, the dsPIC33CH is more competitive; for applications needing a richer analog integration and ecosystem, the C2000 wins.
When should I choose DSPIC33CH128MP206-I/MR over a single-core dsPIC33EP?
Choose the DSPIC33CH128MP206-I/MR over a single-core dsPIC33EP when your control loop must run deterministically below 1 microsecond while a communication stack (CAN, USB, Ethernet) shares the same die. The slave core's 200 MHz speed and dedicated PRAM let the control loop remain jitter-free even under heavy master-core interrupt load.
What is the best drop-in replacement for DSPIC33CH128MP206-I/MR?
The best drop-in replacement is the DSPIC33CH128MP206T-I/MR (tape-and-reel packaging variant) or the DSPIC33CH128MP206-E/MR (extended temperature grade) - all share the same 64-pin QFN (9x9) package and pinout. For alternate memory sizes in the same footprint, the DSPIC33CH64MP206-I/MR (64 KB Flash) is pin-compatible but reduces program memory by ~58%.
Where to download DSPIC33CH128MP206-I/MR datasheet PDF?
The official datasheet for DSPIC33CH128MP206-I/MR can be downloaded from the Microchip product page at https://www.microchip.com/en-us/product/dsPIC33CH128MP206. The document covers pinout, electrical characteristics, peripheral modules, and programming model for both master and slave cores.
Where to find DSPIC33CH128MP206-I/MR pinout?
The pinout for DSPIC33CH128MP206-I/MR is documented on page 1 of the Microchip datasheet and shows all 64 QFN pins with pin 1 marked by a dot at the top-left. Key signals include VDD/VSS pairs, the exposed pad (EP) for thermal dissipation, PGECx/PGEDx pairs for ICSP programming, and dedicated high-resolution PWM outputs.
Can the DSPIC33CH128MP206-I/MR replace dsPIC33EP512MU810 in motor control?
Yes, the DSPIC33CH128MP206-I/MR can replace the dsPIC33EP512MU810 in motor-control designs that fit within 152 KB Flash - the dual-core architecture actually improves FOC performance by offloading the current/torque loop to the slave core. However, the package differs (64 QFN vs 100 TQFP), so a PCB redesign is required.
What are the key specifications of DSPIC33CH128MP206-I/MR that engineers should know?
The DSPIC33CH128MP206-I/MR delivers 152 KB Flash, 16 KB RAM, dual-core operation at 100 MHz (master) and 200 MHz (slave), 12-bit ADC with dual sample-and-hold, high-resolution 250 ps PWM, 3.0-3.6 V supply, and -40 C to +85 C industrial temperature range in a 64-pin QFN (9x9). It targets high-performance digital power and motor-control applications per the Microchip datasheet.

엔지니어링 참조 데이터: DSPIC33CH128MP206-I/MR — 비교, 설계 지침 및 규정 준수 정보.

선택 가이드

Choose the DSPIC33CH128MP206-I/MR when your design needs deterministic, sub-microsecond closed-loop control alongside a full communication stack (CAN-FD, USB, Ethernet) on a single chip. The dual-core architecture makes it ideal for digitally-controlled PFC/LLC converters, FOC motor drives, and wireless-power transmitters. Choose the -E/MR variant when the design must operate above 85 C ambient. For designs that fit in fewer pins, the DSPIC33CH128MP205-I/M4 (48-pin) or DSPIC33CH128MP203-I/M5 (36-pin) drop down within the same family while keeping 152 KB Flash. Avoid this part if your application is purely a low-cost single-loop control task - a single-core dsPIC33EP at half the price is more economical. For applications needing rich analog front-end integration, consider TI's C2000 family as an alternative ecosystem.

대체품과의 비교

파라미터 이 제품 DSPIC33CH128MP206T-I/MR DSPIC33CH128MP206-E/MR DSPIC33CH128MP206-I/PT DSPIC33CH128MP205-I/M4 DSPIC33CH128MP203-I/M5
Brand Microchip Technology Microchip Technology Microchip Technology Microchip Technology Microchip Technology Microchip Technology
Package 64-pin QFN (9x9 mm) with EP 64-pin QFN (9x9 mm) - same 64-pin QFN (9x9 mm) - same 64-pin TQFP (10x10 mm) 48-pin uQFN (6x6 mm) 36-pin uQFN (5x5 mm)
Flash Memory 152 KB 152 KB 152 KB 152 KB 152 KB 152 KB
Master Core Speed 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
Slave Core Speed 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
Operating Temperature -40C to +85C (Industrial) -40C to +85C -40C to +125C (Extended) -40C to +85C -40C to +85C -40C to +85C
Pin Count 64 64 64 64 48 36
Functional Safety (FuSa) Yes Yes Yes Yes Yes Yes

주요 차별점

  • True dual-core on a single die (vs Single-core dsPIC33EP512MU810)
  • Same-family pin-compatible extended-temperature variant (vs DSPIC33CH128MP206-E/MR)
  • Integrated high-resolution PWM with 250 ps edge placement (vs External CPLD + MCU approach)

설계 노트

Estimated: At 200 MHz slave core + 100 MHz master core running full code, the QFN-64 EP device dissipates roughly 0.5-0.8 W. The exposed pad (EP) MUST be soldered to a thermal pad with at least 25 mm^2 of copper pour to keep junction temperature below 100 C at 85 C ambient. Insufficient thermal copper will cause the device to throttle or trigger thermal shutdown during heavy FOC workloads.

Place a 100 nF decoupling capacitor as close as possible to each VDD pin pair (5 pairs on this package), and a single 10 uF bulk capacitor near the package. The exposed pad must have at least 9 thermal vias (0.3 mm diameter) connecting to an internal ground plane for heat sinking. Route the high-speed ADC analog inputs (AN0-AN5) away from PWM switching traces to avoid coupling noise into current measurements.

Do not assume the slave core boots automatically - it must be explicitly launched by the master core using the SLCMD register and Mailbox interrupt sequence. Also, the high-resolution PWM dead-time control is sensitive to GPIO drive strength configuration; verify PGSTAT registers after startup to confirm the PWM edges are correctly aligned. Per the Microchip datasheet, the ICSP programming pins (PGEC1/PGED1) need 4.7 kohm pull-up resistors on PGECx for reliable in-circuit programming.

Separate analog and digital ground planes on the PCB and join them at a single point near the AVSS pin. Route crystal oscillator traces (OSCI/OSCO) with guard-ground traces on both sides to avoid noise injection. Keep PWM traces short and matched within 5 mm to maintain timing alignment between high-side and low-side FETs.

규정 준수 정보

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Qualified
무연
Yes
무할로겐
[Data Needed: Halogen-Free Status]
분쟁 광물
Compliant

RoHS and lead-free compliance per Microchip product page. Industrial temperature grade only; the -E/MR variant extends thermal range but is not AEC-Q100 automotive qualified.

데이터 검증일: 2026-09-22 — XAIPART 부품 엔지니어링 팀이 검증하고 관리한 데이터

관련 검색

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관련 부품 & 용어

Microchip Technology DSPIC33CH128MP206-I/MR DSPIC33CH128MP206T-I/MR DSPIC33CH128MP206-E/MR DSPIC33CH128MP206-I/PT DSPIC33CH128MP205-I/M4 DSPIC33CH128MP203-I/M5 DSPIC33CH Digital Signal Controller DSC dsPIC 16-bit MCU dual-core processor QFN-64 RoHS Functional Safety FuSa high-resolution PWM CAN-FD 12-bit ADC FOC motor control digital power supply totem-pole PFC wireless charging field-oriented control
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