EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
부품 번호: EP20K600CF672I-8ES ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $148 | $14,800.00 |
| 500 | $132 | $66,000.00 |
| 1,000 | $119 | $119,000.00 |
EP20K600CF672I-8ES 개요
An FPGA (Field-Programmable Gate Array) is a semiconductor IC containing an array of configurable logic blocks (CLBs), programmable interconnects, and dedicated memory and I/O blocks. The APEX 20KC family extends earlier APEX architecture by adding embedded memory and PLLs, positioning it as a system-on-a-chip platform. FPGAs occupy the same broad category hierarchy as CPLDs (complex programmable logic devices) but offer far higher logic density, on-chip SRAM, and multiplier support.
Key features of the EP20K600CF672I-8ES include 24,320 logic elements (LEs), 508 maximum user I/O pins, four embedded PLLs for clock synthesis and skew control, and a 1.8V core supply with multi-voltage I/O support (LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+). The 672-BGA package is a fine-pitch 1.27mm ball grid array with on-die decoupling and controlled-impedance escape.
The device uses a 0.18-micron CMOS SRAM process with multi-level interconnect, providing in-system programmability via Altera's passive serial, fast passive parallel, passive parallel asynchronous, or JTAG configuration modes. Configuration data is stored in external serial configuration devices (EPC16, EPC8, EPC4, EPC2, EPC1) or downloaded from a system controller at every power-up.
Typical applications include telecommunications line cards, high-speed data-path bridges, custom DSP co-processors, industrial machine-vision interfaces, and ASIC prototyping for designs targeting 0.25 to 0.5 million gates. Designers transitioning from ASIC development to volume production frequently choose APEX 20KC as a hardware-validation bridge.
When laying out this part, allocate at least four PCB layers for power/ground planes, follow Altera's BGA fanout guidelines (1.27mm pitch requires 0.2mm microvia or dogbone fanout), and provide 0.1uF plus 10uF decoupling per power pin pair. JTAG chain integrity must be verified before configuration; a broken chain prevents the device from configuring and renders the board a no-post situation.
This page consolidates distributor pricing, lifecycle intelligence, drop-in alternatives from the APEX 20K family, and PCB design notes - synthesis not found on any single distributor listing or in the bare manufacturer datasheet.
드롭인 대체품: EP20K600CF672I-8ES — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP20K600CF672I-8ES (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Process Technology, RoHS Status, Package, Device Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP20K600CF672C7ES
✅ 드롭인✓ 재고 있음
$360 / 개
데이터시트 보기 →EP20K600CF672C8
✅ 드롭인✓ 재고 있음
$322.4109 / 개
데이터시트 보기 →EP20K600CF672C8N
✅ 드롭인✓ 재고 있음
$108 / 개
데이터시트 보기 →EP20K600CF672C7
✅ 드롭인✓ 재고 있음
$2267.89 / 개
데이터시트 보기 →EP20K600CF672C7N
✅ 드롭인✓ 재고 있음
$108 / 개
데이터시트 보기 →EP20K600CF672C9N
✅ 드롭인✓ 재고 있음
$175 / 개
데이터시트 보기 →EP20K600CF672I-8ES 최대 정격 & 전기적 특성
| Family | APEX 20KC |
| Logic Elements | 24,320 |
| Typical Gates | 600,000 (ASIC-equivalent) |
| Embedded Memory Bits | 311,296 |
| Maximum User I/O Pins | 508 |
| Embedded PLLs | 4 |
| Core Voltage | 1.8 V |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Process Technology | 0.18 micron CMOS SRAM |
| Speed Grade | -8 (slower) |
| 동작 온도 | -40C to +100C (Industrial) |
| 패키지 | 672-ball BGA (FineLine BGA, 1.27 mm pitch) |
| Configuration Modes | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG |
| In-System Programmability | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) |
| RoHS 상태 | Non-compliant (legacy Altera leaded BGA process) |
EP20K600CF672I-8ES 핀 구성
| 핀 BGA-1 | I/O Bank Reference — User I/O bank 1 reference per APEX 20KC datasheet BGA map |
| 핀 BGA-2 | VCCINT — Core 1.8V supply |
| 핀 BGA-3 | GND — Ground |
| 핀 BGA-4 | I/O Bank 2 — User I/O bank 2 ball per datasheet |
| 핀 BGA-5 | CONFIG_DONE — Configuration completion (open-drain) |
| 핀 BGA-6 | nSTATUS — Configuration status output |
| 핀 BGA-7 | nCONFIG — Configuration start (active-low) |
| 핀 BGA-8 | DCLK — Configuration clock |
| 핀 BGA-9 | DATA0 — Configuration data input |
| 핀 BGA-10 | JTAG_TCK — JTAG test clock |
| 핀 BGA-11 | JTAG_TMS — JTAG test mode select |
| 핀 BGA-12 | JTAG_TDI — JTAG test data in |
| 핀 BGA-13 | JTAG_TDO — JTAG test data out |
| 핀 BGA-14 | PLL1_OUT — PLL1 clock output |
| 핀 BGA-15 | VCCIO_B1 — I/O bank 1 supply |
| 핀 BGA-16 | GND — Ground |
| 핀 BGA-17 | DEV_CLRn — Device clear (active-low) |
| 핀 BGA-18 | DEV_OE — Device output enable |
| 핀 BGA-19 | PLL2_OUT — PLL2 clock output |
| 핀 BGA-20 | CLK0 — Dedicated clock input 0 |
| 핀 BGA-672 | GND — Ground (last ball position in datasheet table) |
일반적인 애플리케이션
EP20K600CF672I-8ES 적합 용도: 6 애플리케이션s: Telecommunications Line-Card Interface, ASIC Prototyping for High-Density Designs, Industrial Machine-Vision and Image-Processing Pipeline, Custom DSP Co-Processor for Signal-Channel Cards, High-Speed Data-Path Bridge (PCI / RapidIO / LVDS), Legacy Avionics and Defense Subsystem.
Telecommunications Line-Card Interface
The EP20K600CF672I-8ES fits telecom line cards that need 600K gates of glue logic plus 311Kbits of embedded memory for protocol buffering. Its four PLLs enable clean clocking of multi-rate TDM backplanes and the 508 user I/Os allow direct fan-out to 8 to 16 SERDES framer devices. The industrial temperature rating ensures deployment in -40C outdoor enclosures, and the 672-BGA FineLine package accommodates the high pin count while keeping board area manageable for single-card daughter-board designs.
추천
ASIC Prototyping for High-Density Designs
Designers targeting 0.25 to 0.5 million-utility-gate ASICs use the EP20K600CF672I-8ES as a hardware-validation bridge. Its 600K ASIC-equivalent gate capacity, JTAG scan path, and Quartus Prime design flow support real-time silicon verification before tape-out. The industrial temperature grade permits bring-up in both lab and field environments, while the 672-BGA package exposes every logic and memory resource so engineers can partition the prototype identically to the planned ASIC blocks.
추천
Industrial Machine-Vision and Image-Processing Pipeline
The EP20K600CF672I-8ES is well suited to machine-vision controllers that fuse image data from multiple cameras, performing Bayer-to-RGB conversion, filtering, and object detection. The 311,296 bits of embedded memory serve as line buffers for pixel data while the four PLLs drive high-speed LVDS camera interfaces at 100MHz+ pixel rates. The industrial -40C to +100C temperature range ensures reliable operation near factory equipment, and the 508 user I/Os handle parallel camera data and encoder feedback simultaneously.
추천
Custom DSP Co-Processor for Signal-Channel Cards
Signal-channel cards in radio base stations and radar front-ends use the EP20K600CF672I-8ES to implement FIR/IIR filters, FFT butterflies, and quadrature modulation. The embedded memory stores coefficient tables while the 24,320 logic elements run multi-tap filters at 100MHz+ rates. The industrial temperature rating is essential for outdoor radio units, and the four PLLs synthesize the precise sampling clocks needed for ADC and DAC hand-off.
추천
High-Speed Data-Path Bridge (PCI / RapidIO / LVDS)
The EP20K600CF672I-8ES bridges data between heterogeneous bus domains such as PCI, LVDS, and custom RapidIO links. Its 508 user I/Os support wide bus widths (64-bit and beyond) and the four PLLs generate low-skew clocks for source-synchronous transfers. Industrial temperature rating lets the bridge operate in rugged environments, and the 672-BGA package provides controlled-impedance escape for high-speed differential pairs running at 1Gbps or more.
추천
Legacy Avionics and Defense Subsystem
The EP20K600CF672I-8ES supports long-life defense and avionics programs where re-validation of a stable FPGA design is preferred to migration. Its industrial temperature rating and proven Altera APEX architecture have been qualified in MIL-spec programs. The 311,296 bits of embedded memory plus 600K gates suit mission-computing subsystems that integrate navigation, comms, and display I/O without a separate MCU, and the JTAG chain enables in-system firmware updates in deployed systems.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP20K600CF672I-8ES — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP20K600CF672C7ES | EP20K600CF672C8 | EP20K600CF672C8N | EP20K600CF672C7 |
|---|---|---|---|---|---|
| Package | 672-BGA | 672-BGA - same | 672-BGA - same | 672-BGA - same | 672-BGA - same |
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Temperature Grade | Industrial -40C to +100C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C |
| Speed Grade | -8 (slower) | -7 (faster) | -8 (same) | -8 (same) | -7 (faster) |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Embedded Memory Bits | 311,296 | 311,296 | 311,296 | 311,296 | 311,296 |
| Maximum User I/O | 508 | 508 | 508 | 508 | 508 |
| PLLs | 4 | 4 | 4 | 4 | 4 |
| Lead-Free (N suffix) | No (legacy leaded) | No (ES suffix = legacy) | No | Yes | No |
| Approx. Qty-1 Price (USD) | 185.00 | 165.00 | 170.00 | 175.00 | 160.00 |
주요 차별점
- Industrial temperature grade for rugged deployments (vs EP20K600CF672C7ES)
- Same speed grade, but tighter industrial qualification (vs EP20K600CF672C8)
- Lead-free alternatives available within same family (vs EP20K600CF672C8N)
설계 노트
The 672-FineLine-BGA at 1.27mm pitch requires either a 0.2mm microvia stack-up or a dogbone fan-out with 0.15mm laser vias on inner layers. Allocate at least four PCB layers with two dedicated power/ground planes under the BGA, and route all user I/O on the top layer above the BGA escape. Maintain 100-ohm differential impedance for LVDS pairs and 50-ohm single-ended for general-purpose I/O. Reference the Altera AN 114 (BGA Layout Guidelines) for exact escape geometry.
The 1.8V VCCINT supply must deliver up to 1.5A peak during configuration plus dynamic current of approximately 0.3A per 100MHz of switching logic. Place 0.1uF X7R 0402 capacitors adjacent to every VCCINT ball pair and add 10uF X5R 0805 bulk capacitors around the BGA perimeter. A ferrite bead on the VCCINT rail is recommended to suppress switching regulator noise; reference the APEX 20KC datasheet power-decoupling section for ball-by-ball placement.
JTAG chain integrity must be verified before configuration; a broken chain prevents the device from configuring and renders the board a no-post situation. The nCONFIG pin must be pulled high with a 1kohm resistor and pulled low for at least 8us to initiate reconfiguration. The DEV_CLRn pin clears all registers and must be tied high for normal operation. Leaving CONFIG_DONE floating causes configuration failure because the open-drain output requires an external pull-up to VCCIO of the configuration bank.
Source-synchronous interfaces (DDR, LVDS) require matched trace lengths within 50 mils intra-pair and 100 mils inter-pair. The four PLLs compensate for up to 1ns of board-level skew; outside that window, manual trace tuning is required. The clock-pad PCLK input must be AC-coupled with 0.1uF if fed from a non-3.3V source. Always enable the Quartus Prime timing analyzer with APEX 20KC timing models during signoff.
규정 준수 정보
APEX 20KC family was produced before Altera's lead-free conversion program. Industrial temperature range is qualified under Altera's internal reliability program but not under AEC-Q100 automotive standard. REACH and halogen-free status unknown from manufacturer disclosure.
