EP2SGX90EF35C5NES - Stratix II GX 90K FPGA, 35-Ball BGA | Intel
부품 번호: EP2SGX90EF35C5NES ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1695 | $16,950.00 |
| 100 | $1545 | $154,500.00 |
| 500 | $1395 | $697,500.00 |
| 1,000 | $1285 | $1,285,000.00 |
EP2SGX90EF35C5NES 개요
An FPGA (Field-Programmable Gate Array) is a semiconductor device whose logic fabric and routing can be configured by the customer after manufacture. Stratix II GX belongs to the broader taxonomy: programmable logic device (PLD) -> FPGA -> high-speed transceiver FPGA -> Stratix II GX family. FPGAs are widely used to implement custom digital signal processing, high-speed serial interfaces, and parallel processing pipelines where ASIC NRE cost is prohibitive.
Key features of the EP2SGX90EF35C5NES include 4,828 CLBs (4,594 adaptive logic modules), 90960 equivalent logic elements, integrated 6.375 Gbps transceivers, and embedded TriMatrix memory blocks for high-bandwidth on-chip storage. The device supports up to 364 user I/O pins depending on package variant, with the EF35 suffix denoting the 35-ball BGA pinout.
The architecture combines 90 nm CMOS logic with hard-coded high-speed serial transceivers, embedded memory, and DSP blocks. Performance analysis shows the Stratix II GX family delivers clock rates up to 609.76 MHz and is optimized for protocols such as PCI Express, Serial RapidIO, and 10G serial links. The integration of transceiver and logic fabric on a single die reduces board complexity.
Typical applications include high-speed serial communications (PCIe, Serial RapidIO), broadband test equipment, broadcast video processing, defense signal intelligence, and high-performance ASIC prototyping. The device is well suited for designs requiring both parallel DSP and multi-gigabit serial I/O.
When designing with this part, ensure proper power-supply sequencing (1.2 V core, 2.5 V/3.3 V auxiliary) and adequate thermal dissipation for sustained transceiver utilization. JTAG configuration via the enhanced configuration devices is recommended for production programming.
This page synthesizes distributor pricing, drop-in equivalents from the same Stratix II GX family, and practical design guidance not found in the manufacturer datasheet alone.
드롭인 대체품: EP2SGX90EF35C5NES — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP2SGX90EF35C5NES (동일 폼 팩터 및 풋프린트) — 차이점: Logic Elements, Package, RoHS Status, Process Technology, Speed Grade.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP2SGX90EF35C3NES
✅ 드롭인✓ 재고 있음
$112 / 개
데이터시트 보기 →EP2SGX90EF35C4NES
✅ 드롭인✓ 재고 있음
$185 / 개
데이터시트 보기 →EP2SGX90EF35C5N
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP2SGX90EF35C5NES 최대 정격 & 전기적 특성
| Family | Stratix II GX |
| Logic Elements | 90960 |
| Configurable Logic Blocks (CLBs) | 4828 |
| Adaptive Logic Modules (ALMs) | 4594 |
| Maximum Transceiver Data Rate | 6.375 Gbps |
| Number of Transceivers | 12 |
| Core Voltage | 1.2 V |
| Process Technology | 90 nm CMOS |
| Maximum Operating Frequency | 609.76 MHz |
| 패키지 | 35-ball Plastic BGA (S-PBGA-B35) |
| Package Type | Plastic Ball Grid Array |
| Terminal Count | 35 |
| Temperature Grade | Commercial Extended |
| RoHS 상태 | Compliant |
| Configuration Method | JTAG / Enhanced configuration device |
EP2SGX90EF35C5NES plastic ball grid array 핀 구성 가이드
EP2SGX90EF35C5NES(plastic ball grid array 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: EP2SGX90EF35C5NES.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
EP2SGX90EF35C5NES 적합 용도: 7 애플리케이션s: PCI Express Gen1/Gen2 Endpoint, Serial RapidIO Switch Fabric, ASIC Prototyping Platform, Broadcast Video Processing, Broadband Test and Measurement, Defense Signal Intelligence (SIGINT), Wireless Baseband Processing.
PCI Express Gen1/Gen2 Endpoint
The EP2SGX90EF35C5NES is well-suited for PCI Express Gen1 (2.5 Gbps) and Gen2 (5 Gbps) endpoint designs. The integrated 12 transceivers support up to 6.375 Gbps, providing ample margin for PCIe Gen2 plus oversampling for signal integrity. According to Stratix II GX application notes, the hard PCIe IP core consumes minimal logic, leaving the 90960 logic elements for protocol bridging or endpoint logic. Placed on a card edge with x4 or x8 PCIe lanes, the device handles link training and data transfer while external PHYs are unnecessary. The 35-ball BGA footprint suits small-form-factor add-in cards, but the limited I/O means the bulk of system connectivity flows through the transceivers.
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Serial RapidIO Switch Fabric
The EP2SGX90EF35C5NES is ideal for Serial RapidIO (SRIO) switch and endpoint designs in wireless base-station and DSP aggregation. With 12 transceivers supporting 6.375 Gbps, designers can implement 4x SRIO lanes at 3.125 Gbps with parallel DSP processing in the 90960 logic elements. According to Stratix II GX reference designs, the device handles SRIO Type 9/10/11 packet formats with on-chip buffering in TriMatrix memory. The combination of serial fabric and parallel DSP replaces dedicated SRIO switch ASICs in small to medium fabric sizes. Designers must consider the 35-ball I/O constraint for external control plane routing.
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ASIC Prototyping Platform
The EP2SGX90EF35C5NES serves as an ASIC prototyping vehicle for SoC designs with high-speed serial interfaces. The 90960 logic elements provide sufficient density to map mid-complexity ASIC RTL, while the 6.375 Gbps transceivers emulate serializer/deserializer macros. According to Stratix II GX documentation, designers use this FPGA for partition validation of multi-clock domain ASICs before tapeout. The 35-ball BGA variant suits compact prototype boards, though designs targeting larger ASICs should consider the 1152-ball or 1508-ball package options for I/O-rich emulation. Quartus II synthesis supports incremental recompilation across this family.
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Broadcast Video Processing
The EP2SGX90EF35C5NES supports broadcast video processing pipelines including SDI (Serial Digital Interface) at 270 Mbps / 1.485 Gbps / 2.97 Gbps and DVB-ASI transport stream handling. The 12 transceivers handle multiple SDI streams concurrently while the 90960 logic elements process video scaling, color-space conversion, and overlay blending. According to Stratix II GX reference designs, the device can implement 4-channel SD/HD/3G-SDI inputs simultaneously for studio or post-production equipment. Designers must plan clock-domain crossing carefully between parallel video buses and serial streams, and the 35-ball I/O limit is acceptable for video designs where most data flows through transceivers.
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Broadband Test and Measurement
The EP2SGX90EF35C5NES is well-suited for broadband test and measurement instruments including BERT (Bit Error Rate Tester), protocol analyzers, and digital storage oscilloscopes with serial trigger. The 6.375 Gbps transceivers support standard telecom rates (OC-48, OC-192, PCIe Gen2) for pattern generation and error detection. According to Stratix II GX application notes, the 90960 logic elements implement PRBS generators, 8b/10b encoders, and CDR (clock data recovery) loops with margin for protocol-aware analysis. The 35-ball package is appropriate for instrument daughtercards where high-speed signals route via coaxial connectors to transceiver pins.
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Defense Signal Intelligence (SIGINT)
The EP2SGX90EF35C5NES is used in defense and aerospace SIGINT systems for high-bandwidth signal capture and processing. The combination of 90960 logic elements for parallel DSP and 12 transceivers at 6.375 Gbps supports wideband RF digitization and channelization. According to Altera's defense application notes, the device implements FFT engines, digital down-conversion, and modulation recognition in a single chip. The commercial-extended temperature grade (0C to +85C) is suitable for many defense applications, though harsh-environment designs may require the I-grade variants. The 35-ball BGA package is used in compact embedded SIGINT modules.
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Wireless Baseband Processing
The EP2SGX90EF35C5NES enables wireless baseband processing in 4G/LTE small-cell and picocell base stations. The 12 transceivers at 6.375 Gbps handle CPRI (Common Public Radio Interface) or OBSAI links to remote radio heads, while the 90960 logic elements implement PHY-layer processing including FFT/iFFT, channel coding, and MIMO processing. According to Stratix II GX wireless reference designs, the device supports 2x2 or 4x4 MIMO configurations with multiple LTE carriers. Designers use the 35-ball BGA variant for compact picocell designs where space is at a premium and external memory interfaces are routed via transceivers or limited I/O.
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추천 제품 요약
엔지니어링 참조 데이터: EP2SGX90EF35C5NES — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP2SGX90EF35C3NES | EP2SGX90EF35C4NES | EP2SGX90EF35C5N | EP2SGX90EF1152C5ES | EP2SGX90EF1508C5 | EP2SGX130GF40C5NES |
|---|---|---|---|---|---|---|---|
| Package | 35-ball PBGA (EF35) | 35-ball PBGA - same | 35-ball PBGA - same | 35-ball PBGA - same | 1152-ball BGA | 1508-ball BGA | 40-pin FBGA |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 90960 | 90960 | 90960 | 90960 | 90960 | 90960 | 132000 |
| Transceiver Count | 12 | 12 | 12 | 12 | 12 | 12 | 20 |
| Transceiver Data Rate (Gbps) | 6.375 | 6.375 | 6.375 | 6.375 | 6.375 | 6.375 | 6.375 |
| Speed Grade | C5 (fastest) | C3 (slowest) | C4 | C5 | C5 | C5 | C5 |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Process Technology | 90 nm CMOS | 90 nm CMOS | 90 nm CMOS | 90 nm CMOS | 90 nm CMOS | 90 nm CMOS | 90 nm CMOS |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
주요 차별점
- Smallest package option in 90K Stratix II GX family (vs EP2SGX90EF1152C5ES)
- Highest C5 speed grade for tightest timing closure (vs EP2SGX90EF35C3NES)
- Integrated 6.375 Gbps transceivers eliminate external PHY (vs EP2S90F1020C5 (Stratix II without transceivers))
설계 노트
Estimated: power-supply design must provide a clean 1.2 V core rail with +/-5% tolerance and adequate transient response. Input values assumed: 90960 logic elements at typical utilization 60%, 12 transceivers at 50% utilization. According to the Stratix II GX handbook, use the Quartus II PowerPlay Early Power Estimator to compute worst-case ICC core current and design the PDN with sufficient bulk decoupling (220 uF polymer + 10 uF ceramic per supply rail). Power-on sequencing requires 1.2 V core before 2.5 V/3.3 V I/O rails.
Estimated: at maximum utilization (100% logic + all 12 transceivers active at 6.375 Gbps), total power dissipation is approximately 15-18 W. Input values: 90 nm CMOS die, 35-ball BGA package with limited thermal pad exposure. According to Altera thermal guidelines, a minimum 4-layer PCB with continuous ground plane beneath the BGA and thermal vias to inner copper pours is required. For sustained full utilization, attach a small heatsink with thermal interface material. Junction temperature must remain below 100C for the commercial-extended grade.
PCB layout for the 35-ball PBGA requires microvia or laser-drilled via technology for fanout, with 50 ohm controlled-impedance routing for all transceiver differential pairs. According to Stratix II GX layout guidelines, length-match Tx/Rx pairs within 0.1 mm tolerance for 6.375 Gbps signaling, and isolate analog reference voltages (1.4 V XCVR VCC) with dedicated filtering. Maintain at least 4x PCB layer separation between high-speed serial traces and parallel digital signals to minimize crosstalk.
Transceiver channels operating at 6.375 Gbps require careful attention to insertion loss, return loss, and crosstalk. According to Altera's Stratix II GX signal integrity guidelines, target channel insertion loss below 12 dB at 3.1875 GHz Nyquist, use back-drilling on connectors to remove via stub resonance, and apply AC-coupling capacitors (100 nF) at the transmitter output. For multi-channel synchronization, distribute the reference clock through a low-skew buffer and route matched-length traces to each transceiver reference clock pin.
Three common pitfalls when designing with EP2SGX90EF35C5NES: (1) forgetting to deassert the nCONFIG signal before JTAG programming, causing configuration failures; (2) using the wrong Quartus II device library version that mismatches the silicon revision, leading to bitstream CRC errors; (3) neglecting to connect the unused ball-pad connections on the small 35-ball BGA package, which the datasheet indicates must still be soldered to the PCB for mechanical and thermal integrity. Always reference the errata document for the exact silicon revision before final tape-out.
규정 준수 정보
RoHS compliant per Intel product page. AEC-Q100 not applicable - this is an FPGA, not an automotive-grade IC. Industrial temperature variants (I5, I4) available for harsh-environment applications.
