EP910LC-30T - 24-Macrocell EPLD, 30ns, 5V, PLCC-44 | Altera
부품 번호: EP910LC-30T ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
EP910LC-30T 개요
An EPLD (Erasable Programmable Logic Device) is a type of CPLD (Complex Programmable Logic Device) - a non-volatile, reprogrammable digital logic IC that replaces discrete TTL/CMOS glue logic. The EP910 belongs to Altera's Classic Family, which sits in the hierarchy: programmable logic device -> SPLD/CPLD -> EPLD -> Classic EPLD -> EP910 series. EPLDs typically integrate multiple macrocells (each containing a programmable AND/OR array, flip-flop, and I/O) into a single chip with predictable timing, making them ideal for state machines, address decoding, and bus-interface glue logic.
Key features of the EP910LC-30T include 24 macrocells providing 450 usable gates, a 30 ns pin-to-pin delay enabling operation up to approximately 33.3 MHz, and 36 user I/O pins with bidirectional programmability. The device is fabricated in CMOS technology, supports in-system UV-erasable programming (windowed ceramic variants) or one-time-programmable (OTP) operation, and includes on-board logic test circuitry for AC parameter verification during production flow.
The architecture is built around a programmable AND/OR array feeding 24 flip-flop-equipped macrocells, with output enable and tri-state control per pin. The wide 5 V supply tolerance (4.75 V to 5.25 V) makes it compatible with legacy TTL logic families, while the CMOS process yields low standby current. Programming is performed via the Altera MAX+PLUS II development system, and JTAG-like boundary-scan support is not present on this classic device.
Typical applications include legacy glue logic in industrial control systems, address decoding for microprocessor buses, state-machine controllers, and replacement of multiple TTL packages in legacy equipment. The 30 ns grade is well-suited to systems using 8- and 16-bit microprocessors (8086, 68000, Z80) where I/O wait-state insertion is acceptable.
When designing with this part, confirm that the 30 ns tPD meets your system's clock-period budget after accounting for setup/hold margins. The PLCC-44 socket enables easy prototyping and field replacement, which is one reason the EP910 family remains in demand for maintaining long-lifecycle industrial and military equipment.
This page synthesizes distributor inventory, package-equivalent drop-in alternatives from the Altera Classic EPLD family, and practical design notes not consolidated in the original manufacturer datasheet.
드롭인 대체품: EP910LC-30T — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP910LC-30T (동일 폼 팩터 및 풋프린트) — 차이점: Package, Propagation Delay (tPD), Mounting Type, Family, Supply Voltage (VCC).
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP910LC-30
✅ 드롭인✓ 재고 있음
$22.5 / 개
데이터시트 보기 →EP910LC-25
✅ 드롭인✓ 재고 있음
$2.2 / 개
데이터시트 보기 →EP910LC-35
✅ 드롭인✓ 재고 있음
$18.75 / 개
데이터시트 보기 →EP910ILI-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910ILC-25
✅ 드롭인✓ 재고 있음
$9.95 / 개
데이터시트 보기 →EP910ILC-15
✅ 드롭인✓ 재고 있음
$16.1 / 개
데이터시트 보기 →EP910LC-30T 최대 정격 & 전기적 특성
| Part Number | EP910LC-30T |
| Manufacturer | Altera (Rochester Electronics) |
| Device Family | Classic EPLD |
| Macrocells | 24 |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 30 ns |
| Maximum Operating Frequency | 33.3 MHz |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable / OTP |
| User I/O Pins | 36 |
| 패키지 | 44-pin PLCC (J-lead) |
| 실장 유형 | Surface Mount |
| Programmable Pins | Bidirectional, tri-state |
| Programming Interface | Altera MAX+PLUS II |
| RoHS 상태 | unknown |
| Lead-Free | unknown |
EP910LC-30T 핀 구성
| 핀 1 | I/O — User I/O pin (bidirectional, programmable) |
| 핀 2 | I/O — User I/O pin |
| 핀 3 | I/O — User I/O pin |
| 핀 4 | I/O — User I/O pin |
| 핀 5 | I/O — User I/O pin |
| 핀 6 | I/O — User I/O pin |
| 핀 7 | I/O — User I/O pin |
| 핀 8 | I/O — User I/O pin |
| 핀 9 | I/O — User I/O pin |
| 핀 10 | I/O — User I/O pin |
| 핀 11 | I/O — User I/O pin |
| 핀 12 | VCC — +5V power supply |
| 핀 13 | I/O — User I/O pin |
| 핀 14 | I/O — User I/O pin |
| 핀 15 | I/O — User I/O pin |
| 핀 16 | I/O — User I/O pin |
| 핀 17 | I/O — User I/O pin |
| 핀 18 | I/O — User I/O pin |
| 핀 19 | I/O — User I/O pin |
| 핀 20 | I/O — User I/O pin |
| 핀 21 | I/O — User I/O pin |
| 핀 22 | I/O — User I/O pin |
| 핀 23 | GND — Ground |
| 핀 24 | I/O — User I/O pin |
| 핀 25 | I/O — User I/O pin |
| 핀 26 | I/O — User I/O pin |
| 핀 27 | I/O — User I/O pin |
| 핀 28 | I/O — User I/O pin |
| 핀 29 | I/O — User I/O pin |
| 핀 30 | I/O — User I/O pin |
| 핀 31 | I/O — User I/O pin |
| 핀 32 | I/O — User I/O pin |
| 핀 33 | I/O — User I/O pin |
| 핀 34 | I/O — User I/O pin |
| 핀 35 | I/O — User I/O pin |
| 핀 36 | I/O — User I/O pin |
| 핀 37 | I/O — User I/O pin |
| 핀 38 | I/O — User I/O pin |
| 핀 39 | I/O — User I/O pin |
| 핀 40 | I/O — User I/O pin |
| 핀 41 | I/O — User I/O pin |
| 핀 42 | I/O — User I/O pin |
| 핀 43 | I/O — User I/O pin |
| 핀 44 | VCC — +5V power supply |
일반적인 애플리케이션
EP910LC-30T 적합 용도: 6 애플리케이션s: Legacy Industrial Control Logic, Address Decoding and Bus Interfacing, State Machine Controllers, Military and Aerospace Avionics, Test Equipment and Instrumentation, Telecommunications Line Cards.
Legacy Industrial Control Logic
The EP910LC-30T's 24 macrocells and 30 ns tPD make it a workhorse for legacy industrial control boards built around 8/16-bit microprocessors (Z80, 8086, 68000). Its 450 usable gates replace several discrete TTL packages, simplifying PCB layout and BOM count. The 5 V supply and CMOS process deliver predictable timing that legacy PLCs and motor controllers rely on for deterministic I/O response, while the 44-pin PLCC socket enables fast field replacement.
추천
Address Decoding and Bus Interfacing
The EP910LC-30T excels at address decoding and bus-interface glue logic between microprocessors, memory, and peripherals. Its 36 user I/Os and bidirectional programmability let one EPLD replace an entire decoder-and-latch circuit built from 74LS series TTL. At 30 ns tPD, it easily meets the address-to-chip-select timing budget for 8 MHz 68000 or 10 MHz 8086 systems, eliminating one wait state in many designs.
추천
State Machine Controllers
Each of the EP910LC-30T's 24 macrocells contains a flip-flop, AND/OR array, and tri-state buffer - the textbook building block for FSM (finite state machine) implementation. Engineers use the part to consolidate multiple small state machines (traffic sequencers, protocol handlers, machine-tool steppers) into one chip. The 33.3 MHz internal frequency and 30 ns propagation delay comfortably support asynchronous serial protocols (RS-232, RS-485) at up to 115200 baud.
추천
Military and Aerospace Avionics
The EP910 family has been used for decades in military and aerospace avionics where board redesign is prohibitively expensive. The EP910LC-30T, when sourced through Rochester Electronics or other franchised channels, supports long-term sustainment programs requiring form-fit-function replacement. Its CMOS process, 5 V supply, and 24 macrocells deliver the deterministic timing that DO-254 and MIL-STD-454 design guidelines demand for safety-critical logic.
추천
Test Equipment and Instrumentation
The EP910LC-30T serves as a programmable timing/sequencer core in legacy test and measurement equipment. Its 24 macrocells can implement complex pattern generators, scan controllers, and timing pulse trains without resorting to discrete TTL sequencers. The 30 ns tPD enables precise edge placement at clock rates up to 33 MHz, and the PLCC-44 socket allows quick firmware updates by reprogramming the EPLD in-circuit via MAX+PLUS II.
추천
Telecommunications Line Cards
The EP910LC-30T is found in legacy telecommunications line cards and central-office equipment implementing protocol conversion, framing, and alarm monitoring. With 36 user I/Os and 5 V CMOS logic levels, it directly interfaces to older T1/E1 framers, LIU devices, and alarm relays. The 30 ns propagation delay easily handles 1.544/2.048 MHz T1/E1 framing requirements, and the PLCC socket simplifies board rework during field service calls.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP910LC-30T — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP910LC-30 | EP910LC-25 | EP910LC-35 | EP910ILI-12 | EP910ILC-25 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-44 | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same | PLCC-44 - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 30 ns | 30 ns | 25 ns (faster) | 35 ns (slower) | 12 ns (much faster) | 25 ns (faster) |
| Maximum Frequency | 33.3 MHz | 33.3 MHz | ~40 MHz | ~28.5 MHz | ~83 MHz | ~40 MHz |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Industrial | Industrial |
| Packaging Format | Tape & Reel | Tube/Tray | Tape & Reel | Tape & Reel | Tape & Reel | Tape & Reel |
주요 차별점
- Pin-identical drop-in to EP910LC-30, differing only in packaging format (vs EP910LC-30)
- Faster -25 grade available in the same PLCC-44 footprint (vs EP910LC-25)
- Industrial-temperature drop-in alternatives available with same pinout (vs EP910ILI-12 / EP910ILC-25)
설계 노트
Estimated: at 5 V VCC and typical ICC of ~120 mA (commercial spec), the EP910LC-30T dissipates approximately 0.6 W in operation. Add a 0.1 uF ceramic decoupling capacitor as close as possible to each VCC pin (12 and 44) and a 10 uF bulk tantalum or aluminum electrolytic capacitor near the package. The 5 V supply rail must remain within 4.75 V to 5.25 V (10% tolerance) to maintain the 30 ns tPD specification - brownout conditions will degrade propagation delay by up to 20%.
Estimated: PLCC-44 socket (e.g., 3M 8444-11B1 or equivalent) is strongly recommended for prototyping and field replacement - direct solder mounting makes rework impractical. Place all 36 user I/O traces with controlled impedance if any run exceed 50 mm, and route VCC/GND pairs as adjacent planes. Keep the EP910LC-30T at least 10 mm away from switching power converters to avoid injecting switching noise into the high-impedance CMOS inputs, which would corrupt macrocell configuration at power-up.
Do not assume the EP910LC-30T is a 5 V tolerant device in the modern sense - older CMOS EPLDs can be damaged by voltages above 7 V or by undershoot below -0.5 V on I/O pins. Always use series resistors (100 ohm) on outputs driving long cables or backplanes. Avoid hot-plugging the device into a live socket; the inrush current can latch up the CMOS I/O cells. Finally, never substitute ceramic-package (windowed UV-erasable) variants for OTP applications - the quartz window leaks long-term programming data under humidity cycling.
규정 준수 정보
RoHS/lead-free status is unknown for this part - confirm with the specific distributor lot. Original Altera Classic EPLD family (late 1980s) used Sn/Pb finishes; Rochester Electronics re-releases may include lead-free terminations. Not applicable for AEC-Q100 (this is a logic device, not an automotive analog IC).