EP910LC-25 - 24 Macrocells Classic EPLD | Intel | 25ns
부품 번호: EP910LC-25 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $2.84 | $2.84 |
| 10 | $2.67 | $26.70 |
| 100 | $2.5 | $250.00 |
| 500 | $2.35 | $1,175.00 |
| 1,000 | $2.2 | $2,200.00 |
EP910LC-25 개요
A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device from the late 1980s/early 1990s era, predating modern CPLDs and FPGAs. An EPLD uses EPROM or EEPROM cells to store the configuration and contains a small number of macrocells organized with a fixed AND-OR PLA-style interconnect fabric. In the broader taxonomy, an EPLD sits between a PAL/GAL and a true CPLD, offering more macrocells than simple PALs while remaining simpler than modern SRAM-based FPGAs. The Classic device family targets glue logic, bus decoding, state machines, and address decoding where moderate complexity is required.
Key features of the EP910LC-25 include 24 macrocells of programmable logic, 16 dedicated inputs, 25 ns pin-to-pin propagation delay, and CMOS technology for low power consumption. The device supports in-system programmability via the Altera programming tools of its era and is offered in a plastic-leaded chip carrier (PLCC) surface-mount package.
The EP910LC-25 architecture uses a PLA-style AND-OR array feeding output macrocells with configurable flip-flops. Fabricated on CMOS, the part draws low standby current and is suitable for battery-backed or always-on legacy systems. With 16 dedicated inputs and I/O architecture, it is appropriate for address decoding and small state-machine duties.
Typical applications include legacy glue logic in industrial controllers, address decoding for microprocessor systems (8086, 68k, MIPS), bus arbitration, state machines in telecom backplanes, and replacement of discrete TTL/CMOS logic on older boards. The wide operating voltage range and CMOS design make it suitable for both 5V and mixed-voltage legacy systems.
When designing with this part, note that it is a legacy device with limited modern tool support. Modern Altera/Intel Quartus does not support the Classic family; designers must use archived MAX+PLUS II or classic Altera tools for programming. Verify long-term availability and consider migration paths.
This page consolidates distributor pricing, drop-in alternatives from the same Classic family, and practical design notes for engineers maintaining legacy EP910-based systems or performing long-life-cycle industrial designs.
드롭인 대체품: EP910LC-25 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP910LC-25 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Supply Voltage (VCC), Process Technology, Mounting Type, Propagation Delay (tPD).
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP910LC-30
✅ 드롭인✓ 재고 있음
$22.5 / 개
데이터시트 보기 →EP910LC-35
✅ 드롭인✓ 재고 있음
$18.75 / 개
데이터시트 보기 →EP910LC-20
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910LC-15
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910LC-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP910LC-25 최대 정격 & 전기적 특성
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Propagation Delay (tPD) | 25 ns |
| Dedicated Inputs | 16 |
| 패키지 | 28-pin PLCC (LC suffix) |
| 실장 유형 | Surface Mount |
| Technology | CMOS (EPROM-based) |
| 동작 온도 | 0C to +70C (commercial) |
| Programmable | Yes (EPROM, UV-erasable on windowed variants) |
EP910LC-25 핀 구성
| 핀 1 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 2 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 3 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 4 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 5 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 6 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 7 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 8 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 9 | INPUT — Dedicated input pin |
| 핀 10 | INPUT — Dedicated input pin |
| 핀 11 | INPUT — Dedicated input pin |
| 핀 12 | INPUT — Dedicated input pin |
| 핀 13 | INPUT — Dedicated input pin |
| 핀 14 | INPUT — Dedicated input pin |
| 핀 15 | INPUT — Dedicated input pin |
| 핀 16 | INPUT — Dedicated input pin |
| 핀 17 | INPUT — Dedicated input pin |
| 핀 18 | INPUT — Dedicated input pin |
| 핀 19 | INPUT — Dedicated input pin |
| 핀 20 | INPUT — Dedicated input pin |
| 핀 21 | INPUT — Dedicated input pin |
| 핀 22 | INPUT — Dedicated input pin |
| 핀 23 | INPUT — Dedicated input pin |
| 핀 24 | INPUT — Dedicated input pin |
| 핀 25 | VCC — Positive supply (typically +5V) |
| 핀 26 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 27 | I/O — Bidirectional I/O pin (macrocell) |
| 핀 28 | GND — Ground |
일반적인 애플리케이션
EP910LC-25 적합 용도: 6 애플리케이션s: Legacy Address Decoding for Microprocessor Systems, Industrial Glue Logic Replacement, Bus Arbitration and Control Logic, State Machine Implementation, Telecom Backplane Glue Logic, Long-Life-Cycle Military/Aerospace Avionics.
Legacy Address Decoding for Microprocessor Systems
The EP910LC-25's 24 macrocells and 16 dedicated inputs make it a strong fit for address decoding in 8086, 68k, and early MIPS systems where it can implement chip-select logic for memory and peripheral devices across a 16- or 24-bit address bus. With 25 ns propagation delay and CMOS low-power operation, it provides reliable decoding well within typical memory access time budgets of 1980s and 1990s microprocessor boards. The PLCC-28 package suits legacy through-hole or socketed designs, and its EPROM programmability allows iterative decoding logic updates during board bring-up. Compared to discrete 74LS/74HC TTL decoder trees, a single EP910LC-25 reduces board area, power consumption, and propagation skew across multiple decode outputs.
추천
Industrial Glue Logic Replacement
The EP910LC-25 is widely used in industrial control systems as a single-chip replacement for multiple TTL/CMOS glue-logic gates scattered across legacy PLCs, motor controllers, and process instrument boards. Its 24 macrocells can absorb the function of 5 to 15 standard SSI/MSI logic packages, reducing PCB area, BOM count, and interconnect failure modes. The 25 ns propagation delay supports typical industrial bus rates (parallel I/O, encoder counters, simple serial protocols) with adequate timing margin. CMOS technology ensures low standby current, important for always-on industrial systems. The PLCC-28 package in a socket allows field replacement on long-life industrial equipment where the original parts have become scarce.
추천
Bus Arbitration and Control Logic
The EP910LC-25's PLA-style AND-OR array is well suited to bus arbitration logic in multi-master backplanes such as VME, Multibus, and proprietary industrial buses where grant, request, and busy signals must be decoded and latched. The 24 macrocells can implement an arbitration state machine plus supporting glue logic in a single device. With 25 ns propagation delay and CMOS low-power characteristics, it meets the timing requirements of legacy 8- and 16-bit bus architectures without contributing significant loading or standby current. The PLCC-28 package accommodates both surface-mount and socketed implementations in legacy telecom and industrial backplane equipment.
추천
State Machine Implementation
The EP910LC-25 with 24 macrocells is well-matched to medium-complexity state machines such as serial protocol controllers (UART framing, SPI master/slave logic), stepper-motor sequencers, and printer/plotter control state machines common in legacy equipment. Each macrocell provides a flip-flop with configurable clock, reset, and output enable, allowing efficient FSM implementation with registered outputs. The 25 ns propagation delay supports state-machine clock rates up to approximately 10-15 MHz in practical designs. EPROM programmability supports iterative state-machine debugging and field updates, which is valuable for long-life industrial and military systems still in service.
추천
Telecom Backplane Glue Logic
The EP910LC-25 is used in legacy telecom backplane equipment where it consolidates discrete TTL logic for alarm monitoring, switch-matrix control, and clock-distribution gating. Its 16 dedicated inputs can directly monitor multiple backplane signal lines, while the 24 macrocells implement alarm-aggregation, de-bounce, and priority-encoding logic. With 25 ns propagation delay and CMOS low-power operation, it supports battery-backed telecom systems that demand minimal standby current. The PLCC-28 package's socketed form factor enables field replacement on telecom infrastructure where the EP910LC-25 may already be end-of-life from the OEM but is still required for service continuity.
추천
Long-Life-Cycle Military/Aerospace Avionics
The EP910LC-25 in industrial screening, or its military-grade variant EP910DM-40, supports long-life-cycle avionics platforms and military ground systems that require decades of continued availability. The EP910 family's CMOS EPROM technology provides non-volatile configuration that survives power cycles without external boot memory, an advantage over SRAM-based PLDs of the same era. The 25 ns propagation delay supports legacy MIL-STD-1553, ARINC 429, and discrete avionics bus interfaces at typical data rates. The PLCC-28 package supports standard MIL-spec PCB assembly processes. For active aerospace programs, the EP910DM/883B screened variant is the preferred choice, but the EP910LC-25 itself remains in use in legacy commercial avionics.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP910LC-25 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP910LC-30 | EP910LC-35 | EP910LC-20 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 28-pin PLCC | 28-pin PLCC - same | 28-pin PLCC - same | 28-pin PLCC - same |
| Macrocells | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 25 ns | 30 ns (slower) | 35 ns (slower) | 20 ns (faster) |
| Dedicated Inputs | 16 | 16 | 16 | 16 |
| Technology | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
주요 차별점
- Mid-range Classic EPLD with 24 macrocells and 25 ns tPD (vs EP610LC-25)
- CMOS low-power operation for battery-backed legacy systems (vs EP910DC-30 (TTL-style EP910 variant))
- Standard commercial temperature grade 0C to +70C (vs EP910DM-40 (military -55C to +125C))
설계 노트
The EP910LC-25 is part of the Altera Classic EPLD family and is NOT supported by modern Intel Quartus software. Designers must use legacy Altera MAX+PLUS II or A+PLUS software for design entry, fitting, and programming. The hardware programmer required is an Altera Logic Programmer or Master Programmer with appropriate adapter for the PLCC-28 package. For ongoing production, archive the MAX+PLUS II project files, programmer drivers, and any licensed seat dongles because these legacy tools are not available through Intel's current sales channels.
When sourcing EP910LC-25 from independent distributors, verify lot traceability and date code. As an obsolete EPROM-based device programmed at the factory, the part does not require in-system programming by the OEM customer - the configuration is fixed at Altera/Intel's programming facility. Counterfeit or remarked Classic EPLDs are a known industry risk; always insist on factory-sealed tubes or trays and demand a manufacturer Certificate of Conformance (CoC). For high-reliability applications, screen the parts for retention and DC parametric compliance before board insertion.
Estimated: At CMOS switching frequencies typical of 1990s-era glue logic (below 10 MHz), the EP910LC-25's dynamic power dissipation remains well below 500 mW, and the commercial 0C to +70C rating is adequate for typical industrial enclosures. However, the PLCC-28 package has a higher junction-to-ambient thermal resistance (estimated 50-60 C/W) than modern QFN packages; designers should verify thermal margin in sealed enclosures. EPROM-based Classic EPLDs retain data indefinitely at room temperature, but data retention at elevated temperatures (>125C) is limited; this is not relevant for the LC (PLCC, commercial) variant but matters for DM (DIP, military) variants.
The 28-pin PLCC package has a JEDEC-standard land pattern with 1.27 mm pin pitch, allowing socket-mounting (e.g., 3M Textool or equivalent PLCC sockets) for field replacement on long-life industrial and military systems. When laying out the PCB, place decoupling capacitors (0.1 uF ceramic in parallel with 10 uF tantalum or electrolytic) within 5 mm of the VCC and GND pins (typically pins 25 and 28 in the standard PLCC-28 pinout). For noise-sensitive applications, route the 16 dedicated inputs away from the I/O macrocell outputs to minimize coupling, and provide a ground plane beneath the device for stable logic reference.
규정 준수 정보
Compliance information not provided in Verified Web Data. The EP910 family was designed in the early 1990s, predating RoHS (2006) and REACH regulations; the LC (PLCC) commercial variant is likely non-RoHS. Military-grade DM variants have their own compliance documentation. For new designs requiring RoHS compliance, choose a modern CPLD instead.
