EPC2LC20NU - 1.6Mb ISP Config PROM 20-PLCC | Intel / Altera
부품 번호: EPC2LC20NU ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.8 | $128.00 |
| 100 | $10.95 | $1,095.00 |
| 500 | $9.4 | $4,700.00 |
| 1,000 | $8.2 | $8,200.00 |
EPC2LC20NU 개요
An FPGA configuration PROM is a non-volatile memory device that holds the bitstream used to program a volatile SRAM-based FPGA at every power-up. Because SRAM LUTs lose their configuration when power is removed, every system containing an SRAM FPGA requires an external boot memory - either a configuration PROM, a flash, or a microcontroller that emulates the configuration bus. EPC2-series devices implement Altera's serial configuration protocol (compatible with FPGAs such as APEX, Cyclone, and older families) and are re-programmable in-system via JTAG, removing the need for a stand-alone programmer in production.
Key features of the EPC2LC20NU include 1.6 Mb of usable configuration memory, an industry-standard 4-pin serial configuration interface (nCS, DCLK, DATA, nINIT_CONF), in-system programmability through the IEEE 1149.1 JTAG port, 3.3 V core supply with 5 V tolerant I/O on most pins, and built-in cascading support so multiple EPC2 devices can be daisy-chained to configure FPGAs larger than 1.6 Mb. The J-lead PLCC-20 footprint has been a long-standing Altera configuration standard and matches the land pattern of earlier EPC1 devices.
Technically the EPC2LC20NU is built on a floating-gate CMOS process with on-chip charge pumps to support in-system erase and reprogram cycles without external high voltages. The 4-pin interface lets the host FPGA generate DCLK and read DATA, while a dedicated nINIT_CONF / OE pin releases the bus at power-up or after a reconfiguration event. Programming endurance is rated in the thousands of cycles with data retention measured in decades, allowing field firmware updates.
Typical applications include Altera APEX II, APEX 20K, Mercury, FLEX 10K, ACEX 1K, and Cyclone-series SRAM-based LUT FPGAs in industrial controllers, telecom line cards, and military / aerospace prototypes that still rely on the legacy serial configuration protocol. Designers should pair the EPC2LC20NU with the appropriate Altera Quartus configuration file format and verify that the target FPGA bitstream size does not exceed the 1.6 Mb capacity.
드롭인 대체품: EPC2LC20NU — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPC2LC20NU (동일 폼 팩터 및 풋프린트) — 차이점: Package, Memory Type, Supported FPGA Families, Mounting Type, Cascade Support.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPC2LC20N
✅ 드롭인✓ 재고 있음
$7.4 / 개
데이터시트 보기 →EPC2LC20
✅ 드롭인✓ 재고 있음
$7.2 / 개
데이터시트 보기 →EPC2LC20NA
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$5.5 / 개
데이터시트 보기 →EPC2LC20N-W
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$6.45 / 개
데이터시트 보기 →EPC2LC20ES
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$5.85 / 개
데이터시트 보기 →EPC2LC20NU 최대 정격 & 전기적 특성
| 기능 | In-System Programmable Configuration PROM |
| Memory Density | 1.6 Mbit |
| FPGA Interface | Altera serial (4-pin: nCS, DCLK, DATA, nINIT_CONF) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V |
| I/O Tolerance | 5 V tolerant inputs (per datasheet, except JTAG pins) |
| Programming Method | In-system via IEEE 1149.1 JTAG |
| JTAG Support | Yes (IEEE Std 1149.1 boundary-scan compliant) |
| Cascade Support | Yes - daisy-chain for larger bitstreams |
| Minimum DC Input | -0.3 V (inputs may undershoot to -2.0 V for <20 ns) |
| Maximum Overshoot | 7.0 V for <100 mA and <20 ns |
| 패키지 | 20-pin J-lead PLCC (9x9 mm) |
| 실장 유형 | Surface Mount |
| Lead-Free / RoHS | Non-LEAD / non-RoHS (NU suffix = matte tin Sn finish, not Pb-free) |
| 동작 온도 | 0C to +70C (commercial) |
| Compatibility | Altera APEX 20K, APEX II, Mercury, FLEX 10K, ACEX 1K, Cyclone (legacy serial configuration) |
EPC2LC20NU 핀 구성
| 핀 1 | DATA — Serial configuration data output to FPGA |
| 핀 2 | DCLK — Configuration clock input from FPGA |
| 핀 3 | nCS — Chip select (active low) |
| 핀 4 | OE / nINIT_CONF — Output enable / configuration init (active low) |
| 핀 5 | VCC — 3.3 V core supply |
| 핀 6 | GND — Ground |
| 핀 7 | TDI — JTAG test data in |
| 핀 8 | TMS — JTAG test mode select |
| 핀 9 | TCK — JTAG test clock |
| 핀 10 | TDO — JTAG test data out |
| 핀 11 | NC — Not connected (per datasheet) |
| 핀 12 | NC — Not connected (per datasheet) |
| 핀 13 | NC — Not connected (per datasheet) |
| 핀 14 | NC — Not connected (per datasheet) |
| 핀 15 | GND — Ground |
| 핀 16 | VCC — 3.3 V core supply |
| 핀 17 | NC — Not connected (per datasheet) |
| 핀 18 | NC — Not connected (per datasheet) |
| 핀 19 | NC — Not connected (per datasheet) |
| 핀 20 | NC — Not connected (per datasheet) |
일반적인 애플리케이션
EPC2LC20NU 적합 용도: 6 애플리케이션s: Altera APEX 20K Configuration Boot, Altera FLEX 10K / ACEX 1K Boot Memory, Mercury / APEX II Mid-Density Boot, Original Cyclone Boot Source, Industrial Control with Field Updates, Legacy / Non-RoHS Repair Stock.
Altera APEX 20K Configuration Boot
The EPC2LC20NU's 1.6 Mb capacity matches the configuration bitstream of most APEX 20K and APEX 20KE designs, while its 4-pin serial interface (nCS, DCLK, DATA, nINIT_CONF) directly drives the FPGA's passive serial configuration port. Designers can use a single PROM for EP20K100, EP20K200, and similar densities without cascade logic. The 20-pin J-lead PLCC footprint is a long-standing Altera standard, keeping the boot path identical to EPC1 designs so legacy PCBs can be re-qualified with a minimal firmware change.
추천
Altera FLEX 10K / ACEX 1K Boot Memory
FLEX 10K and ACEX 1K FPGAs use the legacy 4-pin serial configuration interface that EPC2LC20NU was designed for, so the PROM provides a non-volatile boot source for EPF10K100, EPF10K130, and EP1K100 / EP1K130 devices. The 3.3 V VCC aligns with the FLEX/ACEX VCCIO bank and JTAG is shared with the FPGA chain, simplifying in-system field firmware updates. The 9x9 mm PLCC-20 footprint drops onto a footprint originally sized for EPC1 PROMs, allowing legacy boards to be re-used without PCB rework.
추천
Mercury / APEX II Mid-Density Boot
Mercury (EP1M) and APEX II (EP2A) FPGAs in mid-density configurations fit comfortably inside the 1.6 Mb window of the EPC2LC20NU, with the PROM directly clocking data into the FPGA at the FPGAs DCLK pin during power-up. The PROMs nINIT_CONF pin doubles as the FPGA configuration-begin handshake, simplifying BOM and routing. Because the EPC2LC20NU is JTAG programmable, production-line firmware changes can be pushed through the same chain that programs the FPGA.
추천
Original Cyclone Boot Source
The first-generation Cyclone family (EP1C3, EP1C6, EP1C12, EP1C20) uses Altera's legacy serial configuration protocol and is fully compatible with the EPC2LC20NU. Designers pairing EP1C12 or smaller Cyclone devices with a 1.6 Mb PROM get a single-chip boot solution without cascade glue logic. The PROMs 5 V tolerant inputs ease mixed-voltage interfaces with upstream microcontrollers in industrial control boards.
추천
Industrial Control with Field Updates
In-system JTAG programmability of the EPC2LC20NU lets field engineers push firmware updates through the boards existing JTAG header without swapping parts, ideal for industrial controllers, telecom line cards, and remote telemetry units that must be reconfigured in place. The PROMs 0C to +70C commercial temperature range covers most indoor industrial enclosures, and its data-retention spec of 20+ years keeps factory firmware safe across long field deployments.
추천
Legacy / Non-RoHS Repair Stock
Many military, aerospace, and industrial control boards shipped before 2006 use SnPb (non-RoHS) assembly and require non-RoHS configuration PROMs for repair. The EPC2LC20NUs NU terminal finish lets repair depots replace a failed EPC2 with a like-for-like part without breaking the boards original lead-free waiver. Stocking the part in repair kits extends the service life of long-lived systems where re-design is not practical.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPC2LC20NU — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPC2LC20N | EPC2LC20 | EPC2LC20NA | EPC2LC20N-W | EPC2LC20ES |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 20-PLCC (9x9 mm) | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same | 20-PLCC (9x9 mm) - same |
| Memory Density | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit |
| RoHS / Pb-Free | Non-RoHS (NU finish) | RoHS / Pb-free | Non-RoHS | RoHS | RoHS | RoHS |
| JTAG Programming | Yes | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| Configuration Interface | Altera serial (4-pin) | Altera serial (4-pin) | Altera serial (4-pin) | Altera serial (4-pin) | Altera serial (4-pin) | Altera serial (4-pin) |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Cascade Support | Yes (daisy-chain) | Yes (daisy-chain) | Yes (daisy-chain) | Yes (daisy-chain) | Yes (daisy-chain) | Yes (daisy-chain) |
주요 차별점
- Non-RoHS NU terminal finish for legacy repair (vs EPC2LC20N)
- Identical 1.6 Mb capacity and J-lead PLCC-20 footprint as EPC2LC20N (vs EPC2LC20N)
- Pin-compatible with original EPC1 family (vs EPC1LC20)
설계 노트
Place the EPC2LC20NU on the same board side as the target FPGA, with the 4 configuration traces (nCS, DCLK, DATA, nINIT_CONF) routed short and matched within 1 cm to avoid skew at high DCLK rates. Provide a solid ground reference under the PLCC-20 footprint and tie the JTAG pins (TCK, TMS, TDI, TDO) directly to the boards JTAG header with 10 kohm pull-ups on TMS and TDI to keep the chain stable when no programmer is connected.
Do not substitute EPC2LI20N or EPC2LC120N as a drop-in for EPC2LC20NU - they are different densities and the FPGA will fail to detect the configuration PROM correctly. Verify that the bitstream file (.pof/.sof converted to .hex/.rbf) is generated for the correct EPC2 device ID, otherwise the FPGA will report a configuration error at power-up. For RoHS designs, switch to EPC2LC20N instead of NU; do not assume NU is equivalent to N.
Series-terminate DCLK with 33 ohm near the FPGA driver when the configuration clock exceeds 50 MHz, especially on long backplane traces. The DATA line should be DC-coupled and may require a 10 kohm pull-up if the FPGA does not provide an internal bias; an oscilloscope probe on DCLK during power-up will quickly reveal configuration-bus integrity issues.
규정 준수 정보
NU suffix indicates non-RoHS, non-Pb-free terminal finish. Choose EPC2LC20N for RoHS-compliant assemblies.
