LTC2261CUJ-14 - 14-bit 125Msps 1.8V ADC | Analog Devices
부품 번호: LTC2261CUJ-14 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $67.63 | $67.63 |
| 10 | $60.87 | $608.70 |
| 100 | $54.1 | $5,410.00 |
| 500 | $47.34 | $23,670.00 |
| 1,000 | $43.96 | $43,960.00 |
LTC2261CUJ-14 개요
A pipelined ADC is a high-speed successive-staged converter architecture that resolves an analog input over multiple low-resolution pipeline stages, each stage forwarding residual residue and digital data to the next clock edge. This delivers multi-Msps sample rates while trading input latency (typically a few clock cycles) for very low power per conversion. The LTC2261CUJ-14 sits at the high end of Analog Devices' ultralow-power 1.8V 14-bit family, alongside the 105 Msps LTC2260-14 and 80 Msps LTC2259-14, all of which share the same pinout and 40-pin QFN-6x6 footprint.
Key features include an optional clock duty-cycle stabilizer that corrects for non-50% clock duty, shutdown and nap modes for power gating between conversions, a serial SPI port for configuration of modes and output driver behaviour, and pin-compatible 12-bit versions (LTC2261-12 / LTC2260-12 / LTC2259-12) that drop directly onto the same PCB. An integrated high-bandwidth track-and-hold and on-chip references minimise external component count. Transition noise is rated at 1.2 LSB RMS with no missing codes across the operating temperature range.
Typical applications include multicarrier broadband communications receivers, cellular base-station digitiser cards, software-defined radio (SDR) front-ends, cable head-end equipment, and high-speed test instrumentation. The 1.2V to 1.8V CMOS output swing simplifies direct connection to FPGA LVCMOS banks without level shifters, while the LVDS mode enables long-distance backplane routing at full 125 Msps. Pin compatibility with the slower LTC2260-14 and LTC2259-14 lets one PCB support three speed/price tiers by changing only the ADC part number.
드롭인 대체품: LTC2261CUJ-14 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: LTC2261CUJ-14 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Resolution, Input Type, Architecture, Transition Noise.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
LTC2260CUJ-14
✅ 드롭인✓ 재고 있음
$19.4 / 개
데이터시트 보기 →LTC2259CUJ-14
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2261CUJ-12
✅ 드롭인✓ 재고 있음
$18.4 / 개
데이터시트 보기 →LTC2260CUJ-12
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
LTC2261IUJ-14
✅ 드롭인✓ 재고 있음
$26.8 / 개
데이터시트 보기 →LTC2151CUJ-14
✅ 드롭인✓ 재고 있음
$29.1 / 개
데이터시트 보기 →LTC2261CUJ-14 최대 정격 & 전기적 특성
| 분해능 | 14 bit |
| Sample Rate | 125 Msps |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Analog Supply Voltage | 1.8 V (typ) |
| Digital Output Supply | 1.2 V to 1.8 V |
| SNR (Nyquist) | 73.4 dB |
| SFDR (Nyquist) | 85 dB |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS |
| Missing Codes | No missing codes over temperature |
| Output Interface | Full-rate CMOS / DDR CMOS / DDR LVDS (selectable) |
| 동작 온도 범위 | 0C to +70C (commercial C grade) |
| 패키지 | 40-Pin QFN (6mm x 6mm) |
| 실장 유형 | Surface Mount |
| Configuration Interface | Serial SPI port |
| Special Features | Clock duty cycle stabilizer, shutdown mode, nap mode |
| Pin-Compatible Family | LTC2261-14, LTC2260-14, LTC2259-14 (14-bit); 12-bit equivalents (LTC2261-12, LTC2260-12, LTC2259-12) |
LTC2261CUJ-14 핀 구성
| 핀 1 | VDD — Analog 1.8V supply |
| 핀 2 | GND — Analog ground |
| 핀 3 | AIN+ — Differential analog input, positive |
| 핀 4 | AIN- — Differential analog input, negative |
| 핀 5 | GND — Analog ground |
| 핀 6 | VREF — Reference decoupling |
| 핀 7 | REFT — Reference top decoupling |
| 핀 8 | REFB — Reference bottom decoupling |
| 핀 9 | GND — Digital ground |
| 핀 10 | OVDD — Digital output supply (1.2V-1.8V) |
| 핀 11 | GND — Digital ground |
| 핀 12 | CLK+ — Differential clock input, positive |
| 핀 13 | CLK- — Differential clock input, negative |
| 핀 14 | CS — SPI chip select (active low) |
| 핀 15 | SCK — SPI serial clock |
| 핀 16 | SDI — SPI data in |
| 핀 17 | SDO — SPI data out |
| 핀 18 | D0_DOUT0+ — CMOS/LVDS output bit 0 / DOUT0+ |
| 핀 19 | D1_DOUT0- — CMOS/LVDS output bit 1 / DOUT0- |
| 핀 20 | D2_DOUT1+ — CMOS/LVDS output bit 2 / DOUT1+ |
| 핀 21 | D3_DOUT1- — CMOS/LVDS output bit 3 / DOUT1- |
| 핀 22 | D4_DOUT2+ — CMOS/LVDS output bit 4 / DOUT2+ |
| 핀 23 | D5_DOUT2- — CMOS/LVDS output bit 5 / DOUT2- |
| 핀 24 | D6_DOUT3+ — CMOS/LVDS output bit 6 / DOUT3+ |
| 핀 25 | D7_DOUT3- — CMOS/LVDS output bit 7 / DOUT3- |
| 핀 26 | D8_DOUT4+ — CMOS/LVDS output bit 8 / DOUT4+ |
| 핀 27 | D9_DOUT4- — CMOS/LVDS output bit 9 / DOUT4- |
| 핀 28 | D10_DOUT5+ — CMOS/LVDS output bit 10 / DOUT5+ |
| 핀 29 | D11_DOUT5- — CMOS/LVDS output bit 11 / DOUT5- |
| 핀 30 | D12_DOUT6+ — CMOS/LVDS output bit 12 / DOUT6+ |
| 핀 31 | D13_DOUT6- — CMOS/LVDS output bit 13 / DOUT6- |
| 핀 32 | DF — Data format / sync |
| 핀 33 | GND — Digital ground |
| 핀 34 | OVDD — Digital output supply (1.2V-1.8V) |
| 핀 35 | GND — Digital ground |
| 핀 36 | OVDD — Digital output supply (1.2V-1.8V) |
| 핀 37 | ENC+ — Encode input / clock positive (alternate routing) |
| 핀 38 | ENC- — Encode input / clock negative (alternate routing) |
| 핀 39 | SHDN — Shutdown (active low) / nap mode control |
| 핀 40 | GND — Exposed pad / thermal pad, ground |
일반적인 애플리케이션
LTC2261CUJ-14 적합 용도: 6 애플리케이션s: Cellular Base Station Receiver, Software Defined Radio (SDR) Front-End, Cable Head-End Digitiser, Test & Measurement Instrumentation, Medical Imaging (Ultrasound / Beamforming), Industrial Multi-Channel Data Acquisition.
Cellular Base Station Receiver
The LTC2261CUJ-14's 125 Msps sample rate, 73.4 dB SNR, and 85 dB SFDR make it ideal for digitising multicarrier IF signals in cellular base-station receiver cards. Driving the differential analog input from a SAW-filtered IF at 70-140 MHz, the converter preserves weak pilot tones alongside strong data carriers thanks to its high spurious-free dynamic range. According to the Analog Devices datasheet 226114fc, the selectable DDR LVDS outputs route data directly into FPGA LVDS banks for downstream FFT-based channelisation. Power stays around the datasheet's 125 mW envelope, easing thermal design in compact radio modules.
추천
Software Defined Radio (SDR) Front-End
When streaming wideband RF into an FPGA-based SDR platform, the LTC2261CUJ-14 captures up to ~60 MHz of spectrum per Nyquist band at 125 Msps with 14-bit dynamic range, providing enough headroom for amateur-radio, telemetry, and signal-intelligence workloads. Its 1.2V-1.8V output supply matches modern FPGA LVCMOS banks without level shifters, simplifying PCB routing. The SPI port lets the host FPGA reconfigure output modes, duty-cycle stabiliser, and shutdown state on the fly. Combined with its 1.8V analog supply and ultralow-power draw, the part is well suited to portable SDR backpacks and rackmount receivers alike.
추천
Cable Head-End Digitiser
DOCSIS 3.x cable head-end equipment digitises the downstream RF plant across hundreds of MHz of spectrum. The LTC2261CUJ-14's 73.4 dB SNR and 85 dB SFDR across the full Nyquist band allow direct-IF sampling of multiple downstream QAM channels without front-end analog channel-stacking. Its ability to run DDR LVDS at 125 Msps cleanly interfaces with FPGA demodulator blocks on shared backplanes. Per the datasheet, the duty-cycle-stabiliser feature maintains SNR when the upstream clock source is non-50% duty, useful in distributed head-end timing schemes.
추천
Test & Measurement Instrumentation
In bench-top oscilloscopes, spectrum analysers, and arbitrary waveform digitiser cards, the LTC2261CUJ-14 delivers 14-bit resolution at 125 Msps with ±1 LSB typical INL and ±0.3 LSB DNL for accurate pulse and harmonic analysis. The pipelined latency (a few clock cycles) is acceptable for asynchronous sampling scopes where data is post-processed in batches. Its shutdown and nap modes allow the instrument firmware to duty-cycle power when only periodic captures are needed. The 40-QFN 6mm x 6mm package fits easily in 4-channel digitiser mezzanine cards.
추천
Medical Imaging (Ultrasound / Beamforming)
Mid-tier ultrasound beamforming front-ends digitise 12-16 channels of RF at 40-100 Msps per channel. The LTC2261CUJ-14's 73.4 dB SNR and 85 dB SFDR support tissue-harmonic imaging by capturing low-amplitude second-harmonic content with adequate dynamic range, while the pin-compatible LTC2261CUJ-12 supports 12-bit cost-engineered scanners. The 1.8V analog supply suits portable cart-based systems where thermal management matters. SPI-port programmability allows host firmware to optimise per-mode power consumption (full rate for B-mode, nap mode between pulses in M-mode).
추천
Industrial Multi-Channel Data Acquisition
Process-control and vibration-monitoring DAQ systems digitise multi-axis accelerometers and strain-gauge bridges at high sample rates to capture transients. The LTC2261CUJ-14's 14-bit resolution and 125 Msps speed let one converter handle several oversampled channels in rotation, while its shutdown mode reduces idle power between scheduled scan windows. No-missing-codes over the commercial temperature range ensures calibrated accuracy across factory-floor deployments. The 40-QFN package is small enough to populate parallel digitiser banks on a single carrier board.
추천
추천 제품 요약
엔지니어링 참조 데이터: LTC2261CUJ-14 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | LTC2260CUJ-14 | LTC2259CUJ-14 | LTC2261CUJ-12 | LTC2260CUJ-12 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 12 bit |
| Sample Rate | 125 Msps | 105 Msps | 80 Msps | 125 Msps | 105 Msps |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Output Supply (OVDD) | 1.2 V to 1.8 V | 1.2 V to 1.8 V | 1.2 V to 1.8 V | 1.2 V to 1.8 V | 1.2 V to 1.8 V |
| Output Interface | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
주요 차별점
- Highest sample rate in the 14-bit 1.8V ultralow-power family (vs LTC2260CUJ-14 (105 Msps))
- Pin-compatible speed tiering across the 14-bit family (vs LTC2259CUJ-14 (80 Msps))
- Drop-in resolution upgrade/downgrade without re-layout (vs LTC2261CUJ-12 (12-bit))
- Selectable output interface reduces downstream component count (vs LTC2151CUJ-14 (CMOS-only earlier generation))
설계 노트
Use a single-star ground architecture: connect analog and digital grounds at one low-impedance point directly under the exposed thermal pad. Route the differential analog input traces (AIN+, AIN-) as a tightly-coupled 100-ohm differential pair from the input transformer or driver to the ADC, keeping them away from digital output buses. Place the 0.1uF and 10uF VDD/OVDD decoupling capacitors immediately adjacent to each supply pin with vias to the ground plane directly under the cap pad. Estimates: at 125 Msps, switching-induced digital noise couples capacitively into the analog front-end unless the analog ground plane remains unbroken beneath the analog input traces.
Power the analog VDD and digital OVDD from a low-noise LDO (e.g. ADP1740) rather than the bus rail to keep ripple out of the converter reference. The datasheet's spec for analog supply noise rejection requires a clean 1.8V with sub-millivripple for rated SNR; switch-mode pre-regulators must be filtered with ferrites plus Pi LC networks. Estimates: a switching regulator at 100 kHz with 20 mV p-p ripple after filtration will couple to the ADC's reference and degrade SNR by 1-2 dB.
Avoid driving the analog input single-ended - the LTC2261CUJ-14 is designed for differential input, with common-mode and second-order harmonics cancelling only when both AIN+ and AIN- are driven. Use a 1:1 or 1:2 RF transformer (e.g. Mini-Circuits ADT1-1WT) at the input to convert single-ended signal sources to differential while providing DC bias. Also: leaving unused LVDS/CMOS outputs floating can cross-couple into adjacent traces; follow datasheet guidance to set unused outputs to known states via SPI. Estimated: a single-ended drive reduces SNR by 8-10 dB compared to a balanced drive.
Match the differential clock trace (CLK+/CLK-) to 100 ohms and keep it short; clock jitter directly degrades SNR by 6.02 dB per code-bit when jitter exceeds 1ps RMS at 125 Msps. Use the on-chip clock duty-cycle stabilizer to maintain performance even when the source clock has non-50% duty. Estimated: with a 100 MHz clock at 2ps RMS jitter, theoretical SNR ceiling is approximately 78 dB, so budget jitter carefully when cascading from a noisy PLL.
The exposed thermal pad (pin 40) must be soldered to a contiguous PCB ground plane with multiple thermal vias to a copper pour on the back side. Without this, junction temperature can rise beyond 110C and degrade long-term reliability. Estimated: with 125 mW dissipation and a 40-QFN 6x6 mm with 4 thermal vias in a JEDEC EIA/JESD51 test board, theta_JA is approximately 36 C/W; with reduced thermal vias the rating rises to 80+ C/W and can cause derating.
규정 준수 정보
RoHS / lead-free confirmed by #PBF and #TRPBF ordering suffixes in the Analog Devices family ordering information. AEC-Q100 not applicable - this is a converter, not an automotive-grade qualified part; for AEC-Q100 ADCs consult ADI's automotive portfolio.
