PGA207UA - 5MHz Programmable Gain Instrumentation Amp | TI
부품 번호: PGA207UA ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $35.53 | $35.53 |
| 10 | $32.8 | $328.00 |
| 100 | $29.9 | $2,990.00 |
| 500 | $26.5 | $13,250.00 |
| 1,000 | $22.68 | $22,680.00 |
PGA207UA 개요
A programmable gain instrumentation amplifier (PGIA) is a precision differential amplifier whose closed-loop gain is set digitally rather than by external resistors. In the signal-chain hierarchy it sits between sensors and data converters, combining the true instrumentation-amplifier input stage (high common-mode rejection, balanced high-impedance inputs) with gain-switching logic, so a single ADC channel can resolve signals spanning several orders of magnitude.
Key features of the PGA207 include two CMOS/TTL-compatible address lines for gain selection, analog inputs internally protected against overloads up to +/-40V even with the supplies off, and laser-trimmed offset voltage for low drift. A fast 0.01% settling specification allows the gain to be switched between conversions in high-throughput data-acquisition systems without dead time.
Architecturally, the device uses a three-amplifier instrumentation topology with FET input transistors, giving negligible input bias current (100 pA max) for high-source-impedance sensors, a 25 V/us slew rate, and 18 nV/sqrt(Hz) input noise with 75 dB CMRR. Laser trimming at the Burr-Brown production line holds offset voltage to 1.5 mV max, preserving accuracy at the lowest gains.
Typical applications include programmable data-acquisition front ends, dynamic signal ranges from PT100 sensors and strain-gauge bridges, test and measurement instrumentation, and industrial process-control analog front ends feeding 12- to 16-bit ADCs.
When designing, remember the gain lines are logic-level inputs: tie them to clean CMOS/TTL levels and route away from the input traces. The +/-40V input protection removes the need for external clamp diodes in most industrial environments.
This page consolidates distributor pricing, drop-in family alternatives, and engineering design guidance not found in a single manufacturer datasheet page.
드롭인 대체품: PGA207UA — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: PGA207UA (동일 폼 팩터 및 풋프린트) — 차이점: Input Protection, Package.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
PGA206UA
✅ 드롭인✓ 재고 있음
$8.4 / 개
데이터시트 보기 →PGA204UA
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
PGA205UA
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
PGA207UA 최대 정격 & 전기적 특성
| Amplifier Type | Programmable Gain Instrumentation Amplifier |
| Number of Circuits | 1 |
| Internal Amplifiers | 3 |
| Gain Settings | 1, 2, 5, 10 V/V (digitally programmable) |
| Bandwidth | 5 MHz |
| Slew Rate | 25 V/us |
| Input Bias Current | 100 pA max (FET input) |
| Input Offset Voltage | 1.5 mV max (laser-trimmed) |
| CMRR | 75 dB |
| Input Voltage Noise | 18 nV/sqrt(Hz) |
| Input Protection | +/-40 V (functional with supplies off) |
| Supply Voltage Range | +/-4.5 V to +/-18 V |
| Settling to 0.01% | Fast settling (digitally switchable between conversions) |
| Gain Control Interface | 2 address lines, CMOS/TTL compatible |
| 동작 온도 | -40C to +85C |
| 패키지 | 16-SOIC (SOL-16, 0.295 in, 7.50 mm width) |
| 실장 유형 | Surface Mount |
PGA207UA 16-soic (sol-16, 0.295 in, 7.50 mm width) 핀 구성 가이드
PGA207UA(16-soic (sol-16, 0.295 in, 7.50 mm width) 패키지)의 핀 구성입니다. 이 아날로그 부품에는 입력, 출력, 전원 공급 핀이 있습니다. 오프셋 널, 보상, 인에이블 핀 구성은 제조사 데이터시트를 참조하십시오. 신호 컨디셔닝 및 증폭기 회로에 이상적입니다.
다음에 대한 상세 핀아웃 데이터 없음: PGA207UA.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
PGA207UA 적합 용도: 6 애플리케이션s: Data Acquisition Front End, Industrial Process Control, Test and Measurement Instrumentation, Sensor Bridge and Transducer Amplification, Medical and Biomedical Signal Acquisition, Automatic Test Equipment (ATE).
Data Acquisition Front End
The PGA207UA is a natural fit for multiplexed data-acquisition systems whose input signal span is unknown until runtime. Its two CMOS/TTL address lines let a controller select gains of 1, 2, 5, or 10 V/V in under a microsecond, and the 0.01% fast-settling specification means the amplifier stabilizes between ADC conversions, eliminating dead time. The FET input stage draws only 100 pA max bias current, so high-impedance sources such as piezoelectric and pH probes are not loaded. Inputs tolerate +/-40V faults even with supplies off, protecting the front end during field wiring errors. Place the PGA207UA directly before a 12- to 16-bit ADC with a solid analog ground plane and low-impedance gain-line drivers.
추천
Industrial Process Control
In industrial control loops, sensor signals range from millivolt-level thermocouple outputs to several-volt transmitter outputs on the same channel. The PGA207UA's digitally programmable gain of 1 to 10 V/V lets one analog input condition this full span, while the +/-40V input protection survives miswired 24V field lines even with the card unpowered - a common real-world fault. Laser trimming keeps offset at 1.5 mV max, preserving accuracy at low gains, and the -40C to +85C industrial rating covers cabinet environments. Its 75 dB CMRR rejects ground-potential differences between field sensors and the controller. Use gain codes driven from the PLC backplane logic and place RC filtering ahead of the inputs for RF robustness.
추천
Test and Measurement Instrumentation
Bench instruments and automated test equipment benefit from the PGA207UA's 5 MHz bandwidth combined with autoranging gain control. A measurement system can implement coarse autoranging by switching gains of 1, 2, 5, and 10 - the classic decade sequence - keeping signals within the ADC's optimal range and maximizing resolution across four decades. The 25 V/us slew rate supports fast transient capture, and the FET-input 100 pA bias keeps loading negligible on high-impedance probe points. The 16-SOIC surface-mount package suits compact modular instrument architectures. Layout practice: keep the gain-switch address lines on a quiet logic layer, and shield the differential input traces to preserve the 75 dB CMRR at frequency.
추천
Sensor Bridge and Transducer Amplification
Strain-gauge bridges, load cells, and RTD conditioning circuits produce small differential signals superimposed on large common-mode voltages. The PGA207UA's true three-amplifier instrumentation topology with 75 dB CMRR extracts the differential signal while rejecting common-mode noise, and gain steps of 1 through 10 V/V accommodate bridges with different sensitivities on the same board design. The FET input's 100 pA max bias current minimizes bridge loading errors that plague bipolar-input amplifiers, and the 18 nV/sqrt(Hz) noise floor keeps small signals resolvable. Laser-trimmed offset of 1.5 mV max reduces calibration burden at low gains. Place the amplifier close to the bridge and use Kelvin connections for best accuracy.
추천
Medical and Biomedical Signal Acquisition
Biopotential and biomedical sensor channels - ECG front ends, optical sensor readouts, and lab analyzers - require high input impedance, low bias current, and selectable gain to handle signals from microvolts to volts. The PGA207UA's FET inputs (100 pA max) avoid electrode polarization artifacts, its +/-40V input protection provides defibrillation-style fault tolerance in the input network, and gain codes of 1/2/5/10 enable automatic range adjustment for different sensor types on one platform. The 5 MHz bandwidth is far beyond biopotential needs, giving ample margin for filtering. Designers should add patient-isolation and anti-aliasing filtering per applicable medical standards upstream and downstream of the amplifier stage.
추천
Automatic Test Equipment (ATE)
ATE pin electronics and measurement channels must cover wide voltage and impedance ranges with fast, repeatable range switching. The PGA207UA supports this with digital gain selection (1, 2, 5, 10 V/V) that settles to 0.01% quickly enough to switch between test steps without added dwell time, and its +/-40V input protection absorbs operator or fixture faults that would destroy unprotected amplifiers. The laser-trimmed offset and 75 dB CMRR maintain measurement repeatability, while the industrial -40C to +85C rating suits unconditioned rack environments. The 16-SOIC footprint integrates into dense channel cards. Recommended practice: drive the gain lines from latched logic and verify settling with the actual source impedance of your measurement path.
추천
추천 제품 요약
엔지니어링 참조 데이터: PGA207UA — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | PGA206UA | PGA204UA | PGA205UA |
|---|---|---|---|---|
| Package | 16-SOIC (SOL-16, 7.50 mm) | 16-SOIC (SOL-16) - same | 16-SOIC (SOL-16) - same | 16-SOIC (SOL-16) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Temperature Range | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
주요 차별점
- Decimal gain ladder 1/2/5/10 simplifies calibration (vs PGA206UA)
- Input protection up to +/-40V with supplies off (vs PGA204UA)
- FET input with 100 pA max bias current (vs PGA205UA)
설계 노트
Route the two CMOS/TTL gain-select address lines on a quiet logic layer, physically separated from the differential input traces and the output. Gain switching injects charge transients; a series 100 ohm resistor at each address-line pin plus a local 0.1 uF decoupling capacitor suppresses coupling into the sensitive FET input stage. Maintain a solid ground plane under the SOIC-16 and use Kelvin grounding for the reference (REF) pin so gain accuracy is not degraded by IR drops.
Do not substitute PGA206UA for PGA207UA without updating system gain tables: the binary ladder (1/2/4/8) differs from the decimal ladder (1/2/5/10), and firmware that assumes decade gains will mis-scale readings by up to 25%. Similarly, PGA204UA reaches gain 100 - verify ADC full-scale headroom at the highest gain. Although inputs survive +/-40V, sustained overvoltage with supplies off still dissipates power in the internal protection network; limit fault duration in continuous-fault designs.
The +/-4.5V to +/-18V supply range covers +/-5V, +/-12V, and +/-15V rails, but note the output voltage swing scales with the rails chosen. Decouple each supply pin with 0.1 uF ceramic placed within a few millimeters, plus 4.7 uF bulk per rail. With a 5 MHz bandwidth and 25 V/us slew rate, supply-borne noise couples directly into the signal path - a linear regulator or well-filtered rail upstream preserves the 75 dB CMRR. Estimated: at +/-15V supplies and light loads, quiescent dissipation is modest, but verify junction temperature at high-output-load conditions in dense channel cards.
규정 준수 정보
Compliance status not explicitly stated in the retrieved web data; verify against the TI product page and distributor certificates for the specific date code.
