PIC18LC658/CL - 8-Bit 40MHz PIC18C MCU, 32KB EPROM | Microchip
부품 번호: PIC18LC658/CL ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $85 | $85.00 |
| 10 | $78 | $780.00 |
| 100 | $72 | $7,200.00 |
| 250 | $67.5 | $16,875.00 |
| 500 | $64 | $32,000.00 |
PIC18LC658/CL 개요
A PIC microcontroller (MCU) is a compact programmable computer-on-a-chip that integrates a CPU, memory (ROM/RAM/EPROM/Flash), and configurable I/O peripherals on a single silicon die. The PIC18 family sits at the high-performance end of Microchip's 8-bit portfolio, employing a 16-bit instruction word and an 8-bit data path with hardware multiplier to accelerate arithmetic, table-read/table-write operations for lookup-table acceleration, and a vectored interrupt controller supporting prioritized events. PIC MCUs form part of the broader semiconductor taxonomy of embedded controllers and dominate applications where deterministic behavior, low power, and code stability outweigh raw cycle count.
Key features of the PIC18LC658/CL include its 40 MHz operating frequency yielding a 100 ns instruction cycle, integrated ADC, USART, MSSP (SPI/I2C) peripherals, multiple hardware timers, and a flexible 16-bit wide instruction set that delivers C-compiler-friendly density. The windowed CLCC package allows engineers to erase EPROM under UV light during iterative firmware development.
The device is built on Microchip's 0.8-micron EPROM process with a low-power CMOS core, yielding sleep currents in the microampere range. The architecture emphasizes a 77 instruction set with direct, indirect, and relative addressing modes, plus a hardware multiply/divide unit.
Typical applications include industrial control and instrumentation, CAN bus node prototyping, sensor interface boards, automotive telematics development (CAN-based), and legacy embedded systems undergoing firmware refresh. The 52 I/O pins easily drive LCD controllers, keypads, parallel ADC banks, and motor-control peripherals.
When designing with this device, pay attention to clock source selection (external crystal or oscillator, no internal RC) and configure the configuration-word bits carefully because EPROM devices cannot be bulk-erased in-circuit. Use the UV window only when reworking pre-production firmware.
This page synthesizes distributor pricing, drop-in PIC18 alternative pinouts, and practical design notes not found in the bare manufacturer datasheet, helping procurement and firmware teams evaluate lifecycle risk and second-source options.
드롭인 대체품: PIC18LC658/CL — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: PIC18LC658/CL (동일 폼 팩터 및 풋프린트) — 차이점: Core Architecture, Mounting Type, Operating Temperature, Program Memory Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
PIC18C658-I/LZ
✅ 드롭인 ⚠️ 사양 미검증📋 참조 대체품 (카탈로그에 없음)
PIC18C658-I/PT
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$5.45 / 개
데이터시트 보기 →AT89C51RC2
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
PIC18LC658/CL 최대 정격 & 전기적 특성
| Product Family | PIC® 18C |
| Core Architecture | 8-bit PIC RISC |
| Core Size | 8-bit |
| 최대 클록 주파수 | 40 MHz |
| Program Memory Type | EPROM (OTP, UV-erasable via window) |
| Program Memory Size | 32 KB (16K x 16) |
| RAM Size | 1536 bytes (1.5K x 8) |
| Number of I/O Pins | 52 |
| Package Type | 68-CLCC Window (CERQUAD, 24.13 x 24.13 mm) |
| Operating Voltage Range | 2.5 V to 5.5 V (3.3 V / 5 V operation) |
| Oscillator Type | External (crystal/resonator) |
| 실장 유형 | Through-Hole (windowed ceramic) |
| 동작 온도 | 0 C to +70 C (commercial windowed variant) |
| Instruction Set | PIC18C RISC, 16-bit instruction word |
| Instruction Cycle Time | 100 ns at 40 MHz |
| Peripherals | USART, MSSP (SPI/I2C), ADC, Timers |
| MSL 레벨 | Not applicable (through-hole, not moisture-sensitive) |
| Lead Finish | Tin-lead (SnPb) typical for ceramic development parts |
PIC18LC658/CL 핀 구성
| 핀 1 | OSC1 — Crystal/oscillator input |
| 핀 2 | OSC2 — Crystal/oscillator output |
| 핀 3 | MCLR — Master Clear reset input (active low) |
| 핀 4 | RA0/AN0 — PORTA bit 0 / analog input 0 |
| 핀 5 | RA1/AN1 — PORTA bit 1 / analog input 1 |
| 핀 6 | RA2/AN2 — PORTA bit 2 / analog input 2 |
| 핀 7 | RA3/AN3/VREF — PORTA bit 3 / analog input 3 / voltage reference |
| 핀 8 | RA4/AN4 — PORTA bit 4 / analog input 4 |
| 핀 9 | RA5/AN5 — PORTA bit 5 / analog input 5 |
| 핀 10 | VSS — Ground |
| 핀 11 | RA6/OSC1_EXT — PORTA bit 6 / alternate external clock input |
| 핀 12 | RA7/OSC2_OUT — PORTA bit 7 / alternate clock output |
| 핀 13 | RB0/INT0 — PORTB bit 0 / external interrupt 0 |
| 핀 14 | RB1/INT1 — PORTB bit 1 / external interrupt 1 |
| 핀 15 | RB2/INT2 — PORTB bit 2 / external interrupt 2 |
| 핀 16 | RB3/INT3 — PORTB bit 3 / external interrupt 3 |
| 핀 17 | RB4 — PORTB bit 4 (interrupt-on-change) |
| 핀 18 | RB5 — PORTB bit 5 (interrupt-on-change) |
| 핀 19 | RB6 — PORTB bit 6 (interrupt-on-change / ICSP clock) |
| 핀 20 | RB7 — PORTB bit 7 (interrupt-on-change / ICSP data) |
| 핀 21 | VDD — Positive supply voltage |
| 핀 22 | VSS — Ground |
| 핀 23 | RC0/T1OSO/T1CKI — PORTC bit 0 / Timer1 output / clock input |
| 핀 24 | RC1/T1OSI/CCP2 — PORTC bit 1 / Timer1 input / CCP2 module |
| 핀 25 | RC2/CCP1 — PORTC bit 2 / CCP1 module |
| 핀 26 | RC3/SCK/SCL — PORTC bit 3 / MSSP SPI clock / I2C clock |
| 핀 27 | RC4/SDI/SDA — PORTC bit 4 / MSSP SPI data in / I2C data |
| 핀 28 | RC5/SDO — PORTC bit 5 / MSSP SPI data out |
| 핀 29 | RC6/TX/CK — PORTC bit 6 / USART TX / clock |
| 핀 30 | RC7/RX/DT — PORTC bit 7 / USART RX / data |
| 핀 31 | RD0 — PORTD bit 0 |
| 핀 32 | RD1 — PORTD bit 1 |
| 핀 33 | RD2 — PORTD bit 2 |
| 핀 34 | RD3 — PORTD bit 3 |
| 핀 35 | RD4 — PORTD bit 4 |
| 핀 36 | RD5 — PORTD bit 5 |
| 핀 37 | RD6 — PORTD bit 6 |
| 핀 38 | RD7 — PORTD bit 7 |
| 핀 39 | VDD — Positive supply voltage |
| 핀 40 | VSS — Ground |
| 핀 41 | RE0/RD_BAR — PORTE bit 0 / parallel port read strobe |
| 핀 42 | RE1/WR_BAR — PORTE bit 1 / parallel port write strobe |
| 핀 43 | RE2/CS_BAR — PORTE bit 2 / parallel port chip select |
| 핀 44 | RE3 — PORTE bit 3 |
| 핀 45 | RE4 — PORTE bit 4 |
| 핀 46 | RE5 — PORTE bit 5 |
| 핀 47 | RE6 — PORTE bit 6 |
| 핀 48 | RE7 — PORTE bit 7 |
| 핀 49 | VDD — Positive supply voltage |
| 핀 50 | VSS — Ground |
| 핀 51 | RF0 — PORTF bit 0 |
| 핀 52 | RF1 — PORTF bit 1 |
| 핀 53 | RF2 — PORTF bit 2 |
| 핀 54 | RF3 — PORTF bit 3 |
| 핀 55 | RF4 — PORTF bit 4 |
| 핀 56 | RF5 — PORTF bit 5 |
| 핀 57 | RF6 — PORTF bit 6 |
| 핀 58 | RF7 — PORTF bit 7 |
| 핀 59 | RG0 — PORTG bit 0 |
| 핀 60 | RG1 — PORTG bit 1 |
| 핀 61 | RG2 — PORTG bit 2 |
| 핀 62 | RG3 — PORTG bit 3 |
| 핀 63 | RG4 — PORTG bit 4 |
| 핀 64 | AVDD — Analog positive supply voltage |
| 핀 65 | AVSS — Analog ground |
| 핀 66 | VREF+ — Analog positive voltage reference |
| 핀 67 | VREF- — Analog negative voltage reference |
| 핀 68 | NC/RESERVED — Reserved pin (per datasheet, no connect) |
일반적인 애플리케이션
PIC18LC658/CL 적합 용도: 6 애플리케이션s: Industrial Motor Control Development, CAN Bus Node Prototyping, Legacy Avionics Test Fixtures, Sensor Data Logger Board, Industrial LCD Keypad HMI Module, Educational Engineering Lab Board.
Industrial Motor Control Development
The PIC18LC658/CL enables legacy industrial motor-control firmware prototyping with 52 digital I/O pins driving TRIAC interfaces, encoder inputs, and PWM channels, all coordinated by the 40 MHz PIC18C core. According to data sheet DS30475, the device integrates multiple 16-bit timers and a 10-bit ADC sufficient for closed-loop current sensing at kHz PWM rates. The windowed CLCC package lets engineers erase and re-flash firmware during iterative tuning of speed PI loops and brushless DC commutator tables without re-spinning the PCB.
추천
CAN Bus Node Prototyping
The PIC18LC658/CL is suitable for CAN bus node development where its 52 I/O lines are routed to MCP2510/2551 external CAN controller chips via SPI, while the on-chip MSSP peripheral handles SPI transactions at MHz rates. With 32 KB of EPROM and 1536 bytes of RAM, the MCU supports a CANopen or DeviceNet stack in development environments prior to migrating production firmware to PIC18F variants. Per data sheet DS30475, USART plus MSSP provides sufficient baud-rate flexibility for CAN-to-serial bridge applications.
추천
Legacy Avionics Test Fixtures
Avionics bench-test fixtures (not flight hardware) leverage the PIC18LC658/CL windowed ceramic package to allow UV erasure on each test campaign, replacing firmware to emulate various sensor-failure scenarios. The 68-CERQUAD package is industry-standard for ATE gear in defense testing. The 40 MHz core executes Mil-Std-1553 simulation routines within tight cycle budgets, while the EPROM endurance is sufficient for thousands of erase/program cycles in lab environments.
추천
Sensor Data Logger Board
The PIC18LC658/CL integrates 5 timers and up to 8 ADC channels in a 52 I/O pin budget that supports 4-20 mA current-loop transducer interfaces via ADC plus interrupt-driven end-of-conversion routines. The 32 KB EPROM stores the data acquisition control program plus a small ring buffer of sensor samples before SPI-based FRAM dump. Field-deployed data loggers typically migrate to PIC18F2525 for production because Flash erase simplifies calibration firmware updates without removing the unit from service.
추천
Industrial LCD Keypad HMI Module
The PIC18LC658/CL drives character LCDs and 4x4 matrix keypads through its 52 digital I/O lines, supported by the 40 MHz PIC18C core to sustain debounced scan rates and LCD update vectors without jitter. Per data sheet DS30475, the 32 KB EPROM stores English/Chinese font lookup tables, while MSSP SPI drives the LCD controller over synchronous serial. Production deployments pair the development windowed MCU with a smaller-pin-count Flash successor once the HMI code is finalised.
추천
Educational Engineering Lab Board
The PIC18LC658/CL has been used extensively in university microcontrollers labs because its windowed ceramic package lets students erase and re-program dozens of times across a single semester's lab schedule. Per data sheet DS30475, the 40 MHz PIC18C core, 32 KB EPROM, and 52 I/O pins cover a full range of lab topics from GPIO toggling to USART-serial communication and ADC sampling. Instructors migrate lab manuals to PIC18F45K22 for new cohorts where Flash erase removes the dependency on UV erasers.
추천
추천 제품 요약
엔지니어링 참조 데이터: PIC18LC658/CL — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | PIC18C658-I/LZ | PIC18C658-I/P | PIC18F6520-I/PT | PIC18F6720-I/PT | AT89C51RC2 |
|---|---|---|---|---|---|---|
| Package | 68-CLCC Window (CERQUAD 24.13 x 24.13) | 68-PLCC ceramic (no UV window) | 68-PLCC plastic OTP | 64-TQFP (different package, not drop-in) | 64-TQFP (different package, not drop-in) | 68-PLCC ceramic (different core) |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Program Memory Type | EPROM (UV-erasable, windowed) | EPROM (ceramic, no window) | EPROM (plastic OTP) | Flash (in-circuit erase) | Flash (in-circuit erase) | Flash |
| Program Memory Size | 32 KB (16K x 16) | 32 KB | 32 KB | 32 KB | 128 KB | 32 KB |
| RAM Size | 1.5 KB (1536 bytes) | 1.5 KB | 1.5 KB | 2 KB | 3.84 KB | 1.25 KB |
| Number of I/O Pins | 52 | 52 | 52 | 53 | 68 | 34 |
| Maximum Clock Frequency | 40 MHz | 40 MHz | 40 MHz | 40 MHz | 40 MHz | 40 MHz |
| Oscillator Type | External (crystal) | External (crystal) | External (crystal) | Internal RC + external selectable | Internal RC + external selectable | Internal + external selectable |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Active | Active | Active |
| Operating Voltage Range | 2.5 V to 5.5 V | 2.5 V to 5.5 V | 2.5 V to 5.5 V | 2.0 V to 5.5 V (Flash dies use lower Vin) | 2.0 V to 5.5 V | 2.7 V to 5.5 V |
주요 차별점
- Windowed ceramic package supports iterative firmware reprogramming via UV erasure (vs PIC18F6520-I/PT)
- Higher I/O count than 64-pin Flash successors in the same 40 MHz class (vs PIC18F6520-I/PT (64-TQFP))
- Long lifecycle records through military and aerospace lab use (vs AT89C51RC2 (8051 architecture))
- PIC18C RISC architecture with hardware multiplier (vs AT89C51RC2)
설계 노트
EPROM Parts Need UV Erase: The PIC18LC658/CL cannot be electrically erased; it requires UV erasure through the quartz window before re-programming. Estimated: a 6 mW/cm^2 253.7 nm UV lamp at 1 inch for 20 to 30 minutes achieves reliable erase, but verify with a fresh blank check before re-programming. Production designs should avoid the /CL suffix and instead use the /P plastic OTP variant or migrate to Flash-based PIC18F equivalents to remove the UV-erase infrastructure dependency.
Power Supply Decoupling: Place a 100 nF X7R ceramic capacitor within 5 mm of each VDD pin (pins 21, 39, 49 in the 68-CLCC layout), with a single 10 uF tantalum or ceramic bulk capacitor feeding the analog AVdd pin (pin 64). Estimate: total decoupling budget of 5 to 6 capacitors keeps the PIC18LC658/CL within the 2.5 V to 5.5 V core supply budget specified in data sheet DS30475 even during I/O switching transients.
Crystal Selection and Routing: The PIC18LC658/CL requires external crystal across OSC1 (pin 1) and OSC2 (pin 2). Estimated: a fundamental-mode 4 to 20 MHz crystal with two 22 pF loading capacitors placed within 5 mm of the oscillator pins provides reliable startup. Keep the crystal trace guard-grounded and away from PORTA analog lines to avoid coupling digital noise into the 10-bit ADC reference.
ICSP Programming Pin Reservation: For in-circuit serial programming during prototyping, dedicate pins 19 (RB6/ICSP-CLK) and 20 (RB7/ICSP-DAT) with isolation resistors of 100 ohm series plus a 5 kohm pull-down to prevent interference during debug mode. The windowed CLCC package allows UV erasure but the ICSP path lets developers flash firmware without removing the part, complementing UV erase in production-test scenarios.
Configuration Word Programming: Bits in the EPROM configuration word govern clock source, watchdog enable, low-voltage programming, and code-protect on the PIC18LC658/CL. Programming a chip with code-protect enabled before firmware is fully validated bricks the part for any verification, requiring UV erase. Per data sheet DS30475, developers should leave the CP (code-protect) bit unset throughout the prototyping phase and only flip CP after final firmware release.
규정 준수 정보
Windowed 68-CERQUAD packages typically ship with tin-lead (SnPb) finish and predate RoHS conversion. RoHS status inferred to be non-compliant because device was introduced in late 1990s before 2006 RoHS deadline; specific test report not present in provided data. AEC-Q100 not applicable (industrial-grade windowed variant).
