EP1810GC-35 vs EP1810JC-45 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810GC-35 disebabkan oleh Altera dan EP1810JC-45 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP1810GC-35 EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP1810GC-35 EP1810JC-45
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli NRND
Device Type EPLD (Erasable Programmable Logic Device) —
Logic Family Altera Classic EPLD —
Technology CMOS, UV-erasable EPROM cells CMOS, UV-erasable
Kemasan CPGA-68 (Ceramic Pin Grid Array, 68-pin) PLCC-68 (QCCJ, J-Lead, windowed ceramic)
Bilangan Pin 68 —
Propagation Delay (tpd max) 40 ns —
Maximum Inputs 64 —
Maximum Outputs 48 —
Macrocells 16 48
I/O Standard TTL-compatible —
Programming Method UV erasure + EPROM programming —
Suhu Operasi [DATA_NEEDED: operating temperature range] —
Tegangan Pemberi Arus [DATA_NEEDED: VCC range] —
Jenis Pemasangan Through Hole Surface Mount
Status RoHS Not applicable (legacy ceramic package) [DATA_NEEDED: RoHS compliance not stated in verified data]
Lead-Free Status Not applicable —
Manufacturer (current source) Rochester Electronics (authorized Altera EPLD partner) —
Original Manufacturer Altera Corporation (now Intel FPGA) —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — EP1810 (Classic EPLD Family)
Equivalent Gates — 2100 gates
Dedicated Inputs — 12
I/O Pins — 48
Total User I/O — 60
Propagation Delay (tpd) — 45 ns
Frekuensi Klock Maksimum — 33.3 MHz
Maximum Supply Voltage — 5.25 V
Kiraan Pin — 68
Package Code — QCCJ
Temperature Grade — Commercial

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