EP1810GC-35 vs EP1810JC-45 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GC-35 sa pamamagitan ng Altera at EP1810JC-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810GC-35 EP1810JC-45
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili NRND
Device Type EPLD (Erasable Programmable Logic Device) —
Logic Family Altera Classic EPLD —
Technology CMOS, UV-erasable EPROM cells CMOS, UV-erasable
Packhaging CPGA-68 (Ceramic Pin Grid Array, 68-pin) PLCC-68 (QCCJ, J-Lead, windowed ceramic)
Bilang ng Pins 68 —
Propagation Delay (tpd max) 40 ns —
Maximum Inputs 64 —
Maximum Outputs 48 —
Macrocells 16 48
I/O Standard TTL-compatible —
Programming Method UV erasure + EPROM programming —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Volte ng Pagbibigay [DATA_NEEDED: VCC range] —
Uri ng Pagpapasok Through Hole Surface Mount
Tindminan RoHS Not applicable (legacy ceramic package) [DATA_NEEDED: RoHS compliance not stated in verified data]
Lead-Free Status Not applicable —
Manufacturer (current source) Rochester Electronics (authorized Altera EPLD partner) —
Original Manufacturer Altera Corporation (now Intel FPGA) —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — EP1810 (Classic EPLD Family)
Equivalent Gates — 2100 gates
Dedicated Inputs — 12
I/O Pins — 48
Total User I/O — 60
Propagation Delay (tpd) — 45 ns
Maksimum na Taktiko ng Oras — 33.3 MHz
Maximum Supply Voltage — 5.25 V
Bilang ng Pin — 68
Package Code — QCCJ
Temperature Grade — Commercial

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