EP1S25F672C7N vs EP1S20F672C7N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1S25F672C7N disebabkan oleh Altera dan EP1S20F672C7N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1S25F672C7N EP1S20F672C7N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Family Stratix —
Logic Elements (LEs) 25,660 18,460
Logic Array Blocks (LABs) 2,566 —
Embedded Memory Bits 1,944,576 —
Maximum User I/O 473 586
Number of I/O Pins 672 (BGA balls) —
Kemasan 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch 672-FBGA (FineLine BGA)
Process Technology 0.13 µm CMOS 130 nm CMOS
Core Supply Voltage (VCCINT) 1.5 V —
I/O Supply Voltage (VCCIO) [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] —
Suhu Operasi 0 °C to 85 °C (commercial) 0°C to +85°C (commercial)
Jenis Pemasangan Surface Mount Surface Mount
Configuration Method JTAG / Passive Serial / Active Serial —
Aras MSL [DATA_NEEDED: MSL rating] [DATA_NEEDED: moisture sensitivity level]
Status RoHS [DATA_NEEDED: confirm from product page] —
Series — Stratix (first generation)
Family — Stratix
Logic Cells — 18,460
Configurable Logic Blocks (CLBs) — 2,132
Embedded Memory (TriMatrix) — 1,669,248 bits (426 Kbit total)
DSP Blocks — 56 (dedicated 18x18 multipliers)
I/O Banks — [DATA_NEEDED: I/O bank count]
PLLs — Up to 12
Maximum Operating Frequency — 420.17 MHz
Core Voltage — 1.5 V
Package Body Size — 35 mm x 35 mm
Ball Pitch — 1.27 mm
Speed Grade — C7 (-7)
Lead-Free / RoHS — Yes (lead-free finish, RoHS compliant)
Configuration Modes — PS, PPS, FPP, JTAG

Laporan Datasheet & Sumber

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