EP1S25F672C7N vs EP1S20F672C7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25F672C7N sa pamamagitan ng Altera at EP1S20F672C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1S25F672C7N EP1S20F672C7N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Stratix —
Logic Elements (LEs) 25,660 18,460
Logic Array Blocks (LABs) 2,566 —
Embedded Memory Bits 1,944,576 —
Maximum User I/O 473 586
Number of I/O Pins 672 (BGA balls) —
Packhaging 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch 672-FBGA (FineLine BGA)
Process Technology 0.13 µm CMOS 130 nm CMOS
Core Supply Voltage (VCCINT) 1.5 V —
I/O Supply Voltage (VCCIO) [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] —
Temperature na Operasyon 0 °C to 85 °C (commercial) 0°C to +85°C (commercial)
Uri ng Pagpapasok Surface Mount Surface Mount
Configuration Method JTAG / Passive Serial / Active Serial —
Level ng MSL [DATA_NEEDED: MSL rating] [DATA_NEEDED: moisture sensitivity level]
Tindminan RoHS [DATA_NEEDED: confirm from product page] —
Series — Stratix (first generation)
Family — Stratix
Logic Cells — 18,460
Configurable Logic Blocks (CLBs) — 2,132
Embedded Memory (TriMatrix) — 1,669,248 bits (426 Kbit total)
DSP Blocks — 56 (dedicated 18x18 multipliers)
I/O Banks — [DATA_NEEDED: I/O bank count]
PLLs — Up to 12
Maximum Operating Frequency — 420.17 MHz
Core Voltage — 1.5 V
Package Body Size — 35 mm x 35 mm
Ball Pitch — 1.27 mm
Speed Grade — C7 (-7)
Lead-Free / RoHS — Yes (lead-free finish, RoHS compliant)
Configuration Modes — PS, PPS, FPP, JTAG

Mga Datasheets at Resources

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