EP20K100QC240-3N vs EP20K100QC240-3 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K100QC240-3N disebabkan oleh Altera dan EP20K100QC240-3 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP20K100QC240-3 EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 ✓ Aktif

Pengandingan Spesifikasi

Parametr EP20K100QC240-3N EP20K100QC240-3
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Aktif
Device Type FPGA —
Family APEX-20K —
Gate Count 100000 gates —
Logic Cells 4160 cells —
User I/O 189 I/O —
Distributed Memory 53248 bits —
Macrocells 416 macrocells —
Tegangan Pemberi Arus 2.375 V to 2.625 V —
Nominal Supply 2.5 V —
Maximum Frequency 167 MHz —
Suhu Operasi 0 C to 85 C —
Kemasan 240-BFQFP —
Kiraan Pin 240 pins —
Jenis Pemasangan Surface Mount Surface Mount
Fabrication Process 0.15 um all-layer copper-metal process —
Package Pitch 1.27 mm —
Package Dimensions 45 mm x 45 mm —
Status RoHS unknown —
AEC-Q100 not_qualified —
Manufacturer — Altera
FPGA Family — APEX-20K
Number of Logic Elements — 4160 cells
Total RAM Bits — 53248 bits
Number of User I/O — 189
Typical Gate Count — 263000 gates
Core Supply Voltage — 2.5 V
Frekuensi Klock Maksimum — 167 MHz (family rating)
Speed Grade — -3
Technology Process — 0.22 um
Package Type — 240-BFQFP
Bilangan Pin — 240
Gambaran Suhu Operasi — 0 °C to +85 °C (commercial)
Propagation Delay — [DATA_NEEDED: propagation delay timing table]
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration / JTAG Interface — [DATA_NEEDED: configuration and JTAG interface details]
RoHS Compliance — [DATA_NEEDED: RoHS compliance for non-N version]

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga