EP20K100QC240-3N vs EP20K100QC240-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100QC240-3N sa pamamagitan ng Altera at EP20K100QC240-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K100QC240-3N - 100K-Gate APEX-20K FPGA | Altera | Industrial
EP20K100QC240-3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP20K100QC240-3N | EP20K100QC240-3 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Type | FPGA | — |
| Family | APEX-20K | — |
| Gate Count | 100000 gates | — |
| Logic Cells | 4160 cells | — |
| User I/O | 189 I/O | — |
| Distributed Memory | 53248 bits | — |
| Macrocells | 416 macrocells | — |
| Volte ng Pagbibigay | 2.375 V to 2.625 V | — |
| Nominal Supply | 2.5 V | — |
| Maximum Frequency | 167 MHz | — |
| Temperature na Operasyon | 0 C to 85 C | — |
| Packhaging | 240-BFQFP | — |
| Bilang ng Pin | 240 pins | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Fabrication Process | 0.15 um all-layer copper-metal process | — |
| Package Pitch | 1.27 mm | — |
| Package Dimensions | 45 mm x 45 mm | — |
| Tindminan RoHS | unknown | — |
| AEC-Q100 | not_qualified | — |
| Manufacturer | — | Altera |
| FPGA Family | — | APEX-20K |
| Number of Logic Elements | — | 4160 cells |
| Total RAM Bits | — | 53248 bits |
| Number of User I/O | — | 189 |
| Typical Gate Count | — | 263000 gates |
| Core Supply Voltage | — | 2.5 V |
| Maksimum na Taktiko ng Oras | — | 167 MHz (family rating) |
| Speed Grade | — | -3 |
| Technology Process | — | 0.22 um |
| Package Type | — | 240-BFQFP |
| Bilang ng Pins | — | 240 |
| Hanay ng Temperature na Operasyon | — | 0 °C to +85 °C (commercial) |
| Propagation Delay | — | [DATA_NEEDED: propagation delay timing table] |
| Supported I/O Standards | — | [DATA_NEEDED: supported I/O standards] |
| Configuration / JTAG Interface | — | [DATA_NEEDED: configuration and JTAG interface details] |
| RoHS Compliance | — | [DATA_NEEDED: RoHS compliance for non-N version] |