EP3SE260F1152C4L vs EP3SE260F1152C3N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP3SE260F1152C4L disebabkan oleh Intel dan EP3SE260F1152C3N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EP3SE260F1152C4L - Stratix III E FPGA 255K LE 1152-FCBGA | Intel
EP3SE260F1152C4L ⚠ Bahagian terakhir untuk beliIntel
EP3SE260F1152C3N - Stratix III E FPGA, 255K LE, 744 I/O, 1152-FBGA | Intel
EP3SE260F1152C3N ✓ AktifPengandingan Spesifikasi
| Parametr | EP3SE260F1152C4L | EP3SE260F1152C3N |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Aktif |
| Family | Stratix III E | — |
| Logic Elements (LE) | 255,000 | — |
| Adaptive Logic Modules (ALMs) | 10,200 | — |
| Total Embedded Memory | 16,672,768 bits (16.67 Mbit) | — |
| User I/O Pins | 744 | — |
| Process Technology | 65 nm CMOS | 65 nm |
| Core Voltage | 0.9 V | 1.1 V |
| Kemasan | 1152-ball FC-FBGA | 1152-BBGA, FCBGA |
| Suhu Operasi | 0C to +85C (Commercial) | 0 C to +85 C (Commercial) |
| Maximum Frequency | 375 MHz | — |
| Transceivers | Integrated high-speed transceivers | Integrated high-speed transceivers |
| Memory Interfaces | DDR2/DDR3 with hard controllers | — |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | AS, AP, PS, FPP, JTAG |
| Jenis Pemasangan | Surface Mount (BGA) | Surface Mount |
| Status RoHS | Compliant | Compliant |
| Series | — | Stratix III E |
| Logic Elements / Cells | — | 255,000 |
| Embedded Memory Bits | — | 16,672,768 bits |
| Logic Array Blocks (LABs) | — | 10,200 |
| User I/O Count | — | 744 |
| DSP Blocks | — | Yes (dedicated multiplier/accumulator) |
| Embedded Memory Type | — | TriMatrix (true dual-port, FIFO, ROM, RAM) |
| External Memory Support | — | DDR3, DDR2, QDR II+, RLDRAM II |
| Partial Reconfiguration | — | Supported |
| Programmable Power Technology | — | Yes (up to 50% dynamic power reduction) |