EP3SL200H780C4 vs EP3SL200H780C3N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP3SL200H780C4 disebabkan oleh Altera dan EP3SL200H780C3N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP3SL200H780C4 EP3SL200H780C3N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND NRND
Series Stratix III L —
Device Type FPGA - Field Programmable Gate Array —
Logic Elements 200,000 200,000
Number of LABs/CLBs 8000 —
Total RAM Bits 10,901,504 —
Number of I/O 488 —
Number of Gates [DATA_NEEDED: total gate count not in source data] —
Voltage - Supply 0.9 V (core), 1.1 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V (I/O) —
Suhu Operasi 0C to +85C (commercial) 0C to +85C (commercial)
Internal Operating Frequency Up to 800 MHz —
Jenis Pemasangan Surface Mount Surface Mount
Kemasan / Case 780-BBGA, FCBGA —
Supplier Device Package 780-FCBGA —
Process Node 40 nm TSMC 40 nm
Multiplier Count (9-bit) 488 —
Status RoHS Compliant (lead-free) —
Aras MSL [DATA_NEEDED: MSL level] 3
Family — Stratix III L (low-power)
Embedded Memory Bits — 10,901,504 bits
Logic Array Blocks (LABs) — 8,000
User I/Os — 488
Kemasan — 780-Ball FCBGA (HBGA), 29 x 29 mm
Maximum Internal Clock Frequency — 800 MHz
Transceivers — 24 channels, up to 3.75 Gbps
DSP Blocks — 384
Speed Grade — C3 (commercial, -3 speed)
Voltage - Core — 0.9 V / 1.0 V (core, VCC)
Voltage - I/O — 1.2 V to 3.3 V (VCCIO banks)
Lead-Free / RoHS — Yes
Mounting Pitch — 1.0 mm ball pitch
PLLs — 12 (Stratix III PLL array)
Configuration — JTAG IEEE Std 1149.1, passive/active serial

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga