EP3SL200H780C4 vs EP3SL200H780C3N 比較

詳細並排比較 EP3SL200H780C4 由 Altera 與 EP3SL200H780C3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP3SL200H780C4 EP3SL200H780C3N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND NRND
Series Stratix III L —
Device Type FPGA - Field Programmable Gate Array —
Logic Elements 200,000 200,000
Number of LABs/CLBs 8000 —
Total RAM Bits 10,901,504 —
Number of I/O 488 —
Number of Gates [DATA_NEEDED: total gate count not in source data] —
Voltage - Supply 0.9 V (core), 1.1 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V (I/O) —
工作溫度 0C to +85C (commercial) 0C to +85C (commercial)
Internal Operating Frequency Up to 800 MHz —
安裝類型 Surface Mount Surface Mount
封裝 / 外殼 780-BBGA, FCBGA —
Supplier Device Package 780-FCBGA —
Process Node 40 nm TSMC 40 nm
Multiplier Count (9-bit) 488 —
RoHS 狀態 Compliant (lead-free) —
MSL 等級 [DATA_NEEDED: MSL level] 3
Family — Stratix III L (low-power)
Embedded Memory Bits — 10,901,504 bits
Logic Array Blocks (LABs) — 8,000
User I/Os — 488
封裝 — 780-Ball FCBGA (HBGA), 29 x 29 mm
Maximum Internal Clock Frequency — 800 MHz
Transceivers — 24 channels, up to 3.75 Gbps
DSP Blocks — 384
Speed Grade — C3 (commercial, -3 speed)
Voltage - Core — 0.9 V / 1.0 V (core, VCC)
Voltage - I/O — 1.2 V to 3.3 V (VCCIO banks)
Lead-Free / RoHS — Yes
Mounting Pitch — 1.0 mm ball pitch
PLLs — 12 (Stratix III PLL array)
Configuration — JTAG IEEE Std 1149.1, passive/active serial

資料表與資源

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