EP610DC-35 vs EP610DC-25 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610DC-35 disebabkan oleh Altera dan EP610DC-25 disebabkan oleh Rochester Electronics. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP610DC-35 EP610DC-25
Merek Altera Rochester Electronics
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Aktif
Device Type CPLD - Classic EPLD —
Family Altera Classic EP610 Altera Classic EPLD
Macrocells 16 16
Usable Gates 300 —
Propagation Delay (tPD) 35 ns —
Maximum Frequency (fMAX) 28.6 MHz —
Pipelined Data Rate up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V nominal)
Process Technology CMOS —
Program/erase Method UV-erasable (windowed CERDIP) —
Kemasan 24-pin CDIP (windowed CERDIP) 0.300 inch 24-pin CDIP (Ceramic DIP, through-hole)
Jenis Pemasangan Through-Hole (DIP) Through Hole
Suhu Operasi 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] 0 C to +70 C
Manufacturer Originally Altera; today supplied via Rochester Electronics (authorized) —
Status RoHS [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] —
Product Type — EPLD (Erasable Programmable Logic Device)
Equivalent Gates — 300
Maximum Propagation Delay (tPD) — 25 ns
Number of I/O Pins — 22
Number of Dedicated Inputs — 4
Total Pin Count — 24
Technology — CMOS EPROM (UV-erasable)
Programming Method — JEDEC fuse-map / UV-erase
Speed Grade Suffix — -25 (25 ns tPD)

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