EP610DI-25 vs EP610DM-35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610DI-25 disebabkan oleh Intel dan EP610DM-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP610DI-25 | EP610DM-35 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Part Family | Classic EPLD | Classic EPLD |
| Macrocells | 16 | — |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | 24 dedicated I/O (input + bidirectional) |
| Dedicated Inputs | 4 | — |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V (single supply) |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| Kiraan Pin | 24 | — |
| Jenis Pemasangan | Through-Hole (DIP) | — |
| Suhu Operasi | Industrial (per "I" suffix) | — |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Manufacturer | — | Altera (Rochester Electronics authorized stock) |
| Logic Family | — | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | — | 16 |
| Number of Gates | — | 300 |
| Pipelined Data Rate (fMAX) | — | 100 MHz |
| Kemasan | — | 24-pin CDIP (CERDIP) with UV window |
| Temperature Grade (M) | — | Military -55°C to +125°C |
| Programmability | — | UV-erasable, reprogrammable |
| Gambaran Suhu Operasi | — | -55°C to +125°C |
| Aras MSL | — | [DATA_NEEDED: MSL rating] |
| Status RoHS | — | Non-compliant (contains lead, hermetic CERDIP) |