EP610IDC-10 vs EP610DC-30 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610IDC-10 disebabkan oleh Intel dan EP610DC-30 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP610IDC-10 | EP610DC-30 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Device Family | Altera Classic EPLD | — |
| Logic Capacity | 300 usable gates | — |
| Macrocell Count | 16 macrocells | — |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS EPROM |
| Package Type | 24-pin Ceramic DIP (CDIP) | — |
| Dedicated Inputs | 4 | 16 |
| I/O Pins | 20 | 16 (with output enable) |
| Gambaran Suhu Operasi | 0 °C to +70 °C (commercial) | — |
| Programmable Interconnect | Yes (on-chip) | — |
| In-System Programmability | Yes (via MAX+PLUS II) | — |
| Boundary-Scan Test | Yes (per device documentation) | — |
| Status RoHS | [DATA_NEEDED: RoHS status of CDIP-10 variant] | — |
| Jenis Pemasangan | Through-hole | Through-Hole |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP610 (Classic Device Family) |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| Kemasan | — | 24-pin CERDIP (windowed) |
| Speed Grade | — | -30 (30 ns tPD) |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |
| Suhu Operasi | — | Commercial (0C to +70C) |