EP610IDC-10 vs EP610DC-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610IDC-10 sa pamamagitan ng Intel at EP610DC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610IDC-10 EP610DC-30
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Family Altera Classic EPLD —
Logic Capacity 300 usable gates —
Macrocell Count 16 macrocells —
Pin-to-Pin Logic Delay (tpd) 10 ns —
Maximum Counter Frequency (fCNT) 100 MHz —
Supply Voltage (VCC) 5 V (nominal) —
I/O Logic Compatibility 100% TTL emulation —
Technology CMOS, UV-erasable (windowed ceramic) CMOS EPROM
Package Type 24-pin Ceramic DIP (CDIP) —
Dedicated Inputs 4 16
I/O Pins 20 16 (with output enable)
Hanay ng Temperature na Operasyon 0 °C to +70 °C (commercial) —
Programmable Interconnect Yes (on-chip) —
In-System Programmability Yes (via MAX+PLUS II) —
Boundary-Scan Test Yes (per device documentation) —
Tindminan RoHS [DATA_NEEDED: RoHS status of CDIP-10 variant] —
Uri ng Pagpapasok Through-hole Through-Hole
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — EP610 (Classic Device Family)
Macrocells — 16
Logic Expanders — 4 (4 product terms per macrocell)
Usable Gates — 300
Maximum Pipelined Clock Frequency — 100 MHz
Propagation Delay (tPD) — 30 ns
Packhaging — 24-pin CERDIP (windowed)
Speed Grade — -30 (30 ns tPD)
Programmability — UV-erasable, windowed EPROM
Security Bit — Yes (protects design after programming)
Output Modes — Registered and Combinatorial
Temperature na Operasyon — Commercial (0C to +70C)

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