EP610ILC-10 vs EP610DC-25 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610ILC-10 disebabkan oleh Altera dan EP610DC-25 disebabkan oleh Rochester Electronics. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ AktifPengandingan Spesifikasi
| Parametr | EP610ILC-10 | EP610DC-25 |
|---|---|---|
| Merek | Altera | Rochester Electronics |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Aktif |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 | — |
| Dedicated Inputs | 4 | — |
| Tegangan Pemberi Arus | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Kemasan | PLCC-28 (plastic J-lead chip carrier) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Jenis Pemasangan | Surface Mount (PLCC socket or solder) | Through Hole |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | 0 C to +70 C |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Family | — | Altera Classic EPLD |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Technology | — | CMOS EPROM (UV-erasable) |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |