EP610ILC-10 vs EP610DC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILC-10 sa pamamagitan ng Altera at EP610DC-25 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP610ILC-10 | EP610DC-25 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 | — |
| Dedicated Inputs | 4 | — |
| Volte ng Pagbibigay | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Packhaging | PLCC-28 (plastic J-lead chip carrier) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or solder) | Through Hole |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 C to +70 C |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Family | — | Altera Classic EPLD |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Technology | — | CMOS EPROM (UV-erasable) |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |