EP610ILC-10 vs EP610LC-25 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610ILC-10 disebabkan oleh Altera dan EP610LC-25 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP610ILC-10 | EP610LC-25 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 | [DATA_NEEDED: exact I/O count] |
| Dedicated Inputs | 4 | — |
| Tegangan Pemberi Arus | 5 V (single supply) | 5 V ±5% |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Kemasan | PLCC-28 (plastic J-lead chip carrier) | PLCC-28 |
| Jenis Pemasangan | Surface Mount (PLCC socket or solder) | Surface Mount |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED] |
| Family | — | Classic EPLD |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | 100 MHz |
| Pipelined Data Rate | — | Up to 100 MHz |
| Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed package) |