EP610ILC-25 vs EP610JI-30 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610ILC-25 disebabkan oleh Altera dan EP610JI-30 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP610ILC-25 | EP610JI-30 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | Classic EPLD (EP610 series) | Altera Classic EPLD (EP610) |
| Device Type | EEPLD (Electrically Erasable PLD) | UV Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 300 | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | 160 |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | 4 |
| Bidirectional I/O Pins | 16 | — |
| Gambaran Suhu Operasi | 0 C to +70 C (commercial) | — |
| Kemasan | 28-pin PLCC (J-lead) | CQCC28 (windowed ceramic JLCC, J-bend) |
| Jenis Pemasangan | Surface Mount | Surface Mount (JLCC) |
| Process Technology | CMOS, electrically erasable | CMOS |
| Programming Method | In-system, electrically erasable | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Propagation Delay (tpd) | — | 30 ns (max) |
| Pipelined Data Rate | — | Up to 100 MHz |
| I/O Pins | — | 16 |
| External Clocks | — | 2 |
| Tegangan Pemberi Arus | — | 5 V (single supply) |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |
| Suhu Operasi | — | -40C to +85C (industrial, per EP610 family suffix convention) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |