EP610ILC-25 vs EP610JI-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILC-25 sa pamamagitan ng Altera at EP610JI-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610ILC-25 EP610JI-30
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Classic EPLD (EP610 series) Altera Classic EPLD (EP610)
Device Type EEPLD (Electrically Erasable PLD) UV Erasable Programmable Logic Device (EPLD)
Usable Gates 300 —
Macrocells 16 16
Product Terms 160 160
Maximum Operating Frequency (fMAX) 40 MHz —
Pin-to-Pin Propagation Delay (tPD) 25 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Nominal Supply Voltage 5 V —
Total Inputs 20 —
Dedicated Inputs 4 4
Bidirectional I/O Pins 16 —
Hanay ng Temperature na Operasyon 0 C to +70 C (commercial) —
Packhaging 28-pin PLCC (J-lead) CQCC28 (windowed ceramic JLCC, J-bend)
Uri ng Pagpapasok Surface Mount Surface Mount (JLCC)
Process Technology CMOS, electrically erasable CMOS
Programming Method In-system, electrically erasable —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
Propagation Delay (tpd) — 30 ns (max)
Pipelined Data Rate — Up to 100 MHz
I/O Pins — 16
External Clocks — 2
Volte ng Pagbibigay — 5 V (single supply)
Package Code — JLCC-28 / CQCC28
Erasure Method — Ultraviolet (UV) via top window
Programming — Altera Logic Programmer compatible
Temperature na Operasyon — -40C to +85C (industrial, per EP610 family suffix convention)
Lead-Free — [DATA_NEEDED: lead-free status]

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