EP610PC-15 vs EP610JI-30 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610PC-15 disebabkan oleh Altera dan EP610JI-30 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP610PC-15 EP610JI-30
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND NRND
Family Classic EPLD Altera Classic EPLD (EP610)
Device Type EPLD (Erasable Programmable Logic Device) UV Erasable Programmable Logic Device (EPLD)
Usable Gates 300 gates —
Macrocells 16 16
Logic Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) —
Maximum Counter Frequency 100 MHz (per family datasheet) —
Pipelined Data Rate Up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 5 V (single supply) —
Technology CMOS —
Architecture PAL-type, sum-of-products AND/OR array —
TTL Emulation 100% TTL compatible —
Kemasan PDIP-24 (plastic DIP, 24-pin) CQCC28 (windowed ceramic JLCC, J-bend)
Kiraan Pin 24 pins —
Suhu Operasi [DATA_NEEDED: operating temperature range] -40C to +85C (industrial, per EP610 family suffix convention)
Jenis Pemasangan Through-Hole (DIP) Surface Mount (JLCC)
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
Development Tool Altera MAX+PLUS II —
Logic Test Circuitry On-board for AC/DC verification —
Propagation Delay (tpd) — 30 ns (max)
Product Terms — 160
Dedicated Inputs — 4
I/O Pins — 16
External Clocks — 2
Tegangan Pemberi Arus — 5 V (single supply)
Process Technology — CMOS
Package Code — JLCC-28 / CQCC28
Erasure Method — Ultraviolet (UV) via top window
Programming — Altera Logic Programmer compatible
Lead-Free — [DATA_NEEDED: lead-free status]

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