EP910DC-35 vs EP910DM883B Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DC-35 disebabkan oleh Altera dan EP910DM883B disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910DC-35 EP910DM883B
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Type UV-Erasable CMOS PLD (PAL-type) Erasable Programmable Logic Device (EPLD)
Family Classic EPLD EP910 Classic EPLD - EP910 Series
Architecture PAL-type sum-of-products AND-OR array PAL-type AND-OR-NOT, CMOS
Usable Gates 900 gates —
Macrocells 24 24
Product Terms 240 240
Dedicated Inputs 12 —
I/O Pins 24 —
Total Inputs 36 —
Propagation Delay (tpd) 35 ns —
Frekuensi Klock Maksimum 37 MHz (typical, internal) 25 MHz
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) —
Suhu Operasi 0 °C to +70 °C (commercial) -55 °C to +125 °C (military)
Kemasan 40-pin CDIP (Ceramic DIP) with quartz window CDIP-40 (Ceramic DIP, 40-pin)
Lead Pitch 2.540 mm —
Termination Style Through-Hole —
Programming Method JEDEC fuse map via device programmer; UV erase —
Technology CMOS, UV-erasable EPROM cell —
Status RoHS Non-compliant (ceramic DIP with Pb-bearing lead finish) [DATA_NEEDED: RoHS status]
Lifecycle Obsolete / last-time-buy from authorized distributors —
Manufacturer — Altera (now part of Intel)
Inputs — 36
Outputs — 24
Propagation Delay (tPD) — 40 ns (typical)
Supply Voltage (VCC) — 5 V
Programming Voltage (VPP) — 12.5 V (UV-erase window)
Jenis Pemasangan — Through-Hole (DIP)
MIL Processing — MIL-STD-883B Class B
Configuration Memory — UV-erasable EPROM
Logic Elements — Combinational + Registered
Lead-Free — [DATA_NEEDED: lead-free status]

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