EP910DC-35 vs EP910DM883B Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-35 sa pamamagitan ng Altera at EP910DM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DC-35 | EP910DM883B |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | Erasable Programmable Logic Device (EPLD) |
| Family | Classic EPLD EP910 | Classic EPLD - EP910 Series |
| Architecture | PAL-type sum-of-products AND-OR array | PAL-type AND-OR-NOT, CMOS |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | 240 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| Maksimum na Taktiko ng Oras | 37 MHz (typical, internal) | 25 MHz |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | -55 °C to +125 °C (military) |
| Packhaging | 40-pin CDIP (Ceramic DIP) with quartz window | CDIP-40 (Ceramic DIP, 40-pin) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | — |
| Technology | CMOS, UV-erasable EPROM cell | — |
| Tindminan RoHS | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Manufacturer | — | Altera (now part of Intel) |
| Inputs | — | 36 |
| Outputs | — | 24 |
| Propagation Delay (tPD) | — | 40 ns (typical) |
| Supply Voltage (VCC) | — | 5 V |
| Programming Voltage (VPP) | — | 12.5 V (UV-erase window) |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |
| MIL Processing | — | MIL-STD-883B Class B |
| Configuration Memory | — | UV-erasable EPROM |
| Logic Elements | — | Combinational + Registered |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |