EP910DC-40 vs EP910DM883B Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DC-40 disebabkan oleh Altera dan EP910DM883B disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910DC-40 EP910DM883B
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Family Classic EPLD (EP910 series) —
Architecture PAL-type AND/OR, UV-erasable CMOS PAL-type AND-OR-NOT, CMOS
Macrocells 24 24
Dedicated Inputs 12 —
Bidirectional I/O Pins 24 —
Total Inputs to Logic Array 36 —
Product Terms 240 maximum 240
Maximum Propagation Delay (tPD) 40 ns —
Maximum Operating Frequency (fMAX) 25 MHz —
Global Clocks 2 —
Tegangan Pemberi Arus 5 V (typical for Classic EPLD family) —
Operating Temperature (Commercial) 0 °C to 70 °C —
Kemasan DIP-40 (ceramic, through-hole) CDIP-40 (Ceramic DIP, 40-pin)
Jenis Pemasangan Through-Hole Through-Hole (DIP)
Status RoHS [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Programming Method UV-erase + EPROM programmer; on-board logic test circuitry —
Manufacturer — Altera (now part of Intel)
Family — Classic EPLD - EP910 Series
Device Type — Erasable Programmable Logic Device (EPLD)
Inputs — 36
Outputs — 24
Propagation Delay (tPD) — 40 ns (typical)
Frekuensi Klock Maksimum — 25 MHz
Supply Voltage (VCC) — 5 V
Programming Voltage (VPP) — 12.5 V (UV-erase window)
Suhu Operasi — -55 °C to +125 °C (military)
MIL Processing — MIL-STD-883B Class B
Configuration Memory — UV-erasable EPROM
Logic Elements — Combinational + Registered
Lead-Free — [DATA_NEEDED: lead-free status]

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