EP910DC-40 vs EP910DM883B Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-40 sa pamamagitan ng Altera at EP910DM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DC-40 EP910DM883B
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Classic EPLD (EP910 series) —
Architecture PAL-type AND/OR, UV-erasable CMOS PAL-type AND-OR-NOT, CMOS
Macrocells 24 24
Dedicated Inputs 12 —
Bidirectional I/O Pins 24 —
Total Inputs to Logic Array 36 —
Product Terms 240 maximum 240
Maximum Propagation Delay (tPD) 40 ns —
Maximum Operating Frequency (fMAX) 25 MHz —
Global Clocks 2 —
Volte ng Pagbibigay 5 V (typical for Classic EPLD family) —
Operating Temperature (Commercial) 0 °C to 70 °C —
Packhaging DIP-40 (ceramic, through-hole) CDIP-40 (Ceramic DIP, 40-pin)
Uri ng Pagpapasok Through-Hole Through-Hole (DIP)
Tindminan RoHS [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Programming Method UV-erase + EPROM programmer; on-board logic test circuitry —
Manufacturer — Altera (now part of Intel)
Family — Classic EPLD - EP910 Series
Device Type — Erasable Programmable Logic Device (EPLD)
Inputs — 36
Outputs — 24
Propagation Delay (tPD) — 40 ns (typical)
Maksimum na Taktiko ng Oras — 25 MHz
Supply Voltage (VCC) — 5 V
Programming Voltage (VPP) — 12.5 V (UV-erase window)
Temperature na Operasyon — -55 °C to +125 °C (military)
MIL Processing — MIL-STD-883B Class B
Configuration Memory — UV-erasable EPROM
Logic Elements — Combinational + Registered
Lead-Free — [DATA_NEEDED: lead-free status]

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