EP910LI-50 vs EP910LI-20 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910LI-50 disebabkan oleh Altera dan EP910LI-20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910LI-50 EP910LI-20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family Altera Classic EPLD Altera Classic EPLD
Macrocells 24 24
Usable Gates 450 —
Propagation Delay (tPD) 50 ns —
Package Type CERDIP-40 (L) Through-Hole, Ceramic DIP with Quartz Window
Package Pin Count 40 —
Supply Voltage (VCC) 5 V +/- 10% 5 V
Suhu Operasi -40C to +85C (industrial) -40C to +85C (Industrial)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable
Logic Blocks Classic AND/OR array architecture —
I/O Pins [DATA_NEEDED: I/O pin count] 24
Programming Method EPROM programmer (UV-erasable window) —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Speed Grade Suffix -50 (50 ns tPD) —
Maximum Operating Frequency — 62 MHz
Propagation Delay (tpd) — 20 ns
Dedicated Inputs — 16
Kemasan — 40-pin Ceramic DIP (Windowed)
Temperature Grade — Industrial (-40C to +85C)
Kiraan Pin — 40
Logic Family — EPLD (Erasable PLD)
Architecture — Sum-of-products macrocell
Pin/Package Compatibility — Pin-compatible across EP910 family

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